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Ignore ctrl-Zs in preprocessor

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git-svn-id: file://localhost/svn/verilator/trunk/verilator@925 77ca24e4-aefa-0310-84f0-b9a241c72d87
This commit is contained in:
Wilson Snyder 2007-05-17 16:15:24 +00:00
parent 386f0a75df
commit 2c5a183368
3 changed files with 9 additions and 3 deletions
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8
src/V3PreLex.l
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@ -58,12 +58,15 @@ static void pslMoreNeeded(bool flag) { V3PreLex::s_currentLexp->m_pslMoreNeeded
%x ARGMODE
%x INCMODE
/* drop: Drop Ctrl-Z - can't pass thru or may EOF the output too soon */
ws [ \t\f\r]
wsn [ \t\f]
crnl [\r]*[\n]
quote [\"]
backslash [\\]
symb [a-zA-Z_][a-zA-Z0-9_$]*
drop [\032]
psl [p]sl
/**************************************************************/
@ -113,6 +116,7 @@ psl [p]sl
/* Reading definition */
<DEFMODE>"/*" { yy_push_state(CMTMODE); yymore(); }
<DEFMODE>"//"[^\n\r]* { return (VP_COMMENT);}
<DEFMODE>{drop} { }
<DEFMODE><<EOF>> { linenoInc(); yyerror("EOF (missing return?) in define value"); yyleng=0; yyterminate(); }
<DEFMODE>{crnl} { linenoInc(); yy_pop_state(); yytext="\n"; yyleng=1; return (VP_DEFVALUE); }
<DEFMODE>[\\]{crnl} { linenoInc(); appendDefValue("\n",1); } /* Include return so can maintain output line count */
@ -123,6 +127,7 @@ psl [p]sl
/* Define arguments */
<ARGMODE>"/*" { yy_push_state(CMTMODE); yymore(); }
<ARGMODE>"//"[^\n\r]* { return (VP_COMMENT);}
<ARGMODE>{drop} { }
<ARGMODE><<EOF>> { yyerror("EOF in define argument list\n"); yyleng = 0; yyterminate(); }
<ARGMODE>{crnl} { linenoInc(); yytext="\n"; yyleng=1; return(VP_WHITE); }
<ARGMODE>{quote} { yy_push_state(STRMODE); yymore(); }
@ -179,8 +184,9 @@ psl [p]sl
/* Generics */
<INITIAL,PSLMULM>{crnl} { linenoInc(); yytext="\n"; yyleng=1; return(VP_WHITE); }
<INITIAL,PSLMULM,PSLONEM>{symb} { return (VP_SYMBOL); }
<INITIAL,PSLMULM,PSLONEM>[\r] { }
<INITIAL,PSLMULM,PSLONEM>{wsn}+ { return (VP_WHITE); }
<INITIAL,PSLMULM,PSLONEM>{drop} { }
<INITIAL,PSLMULM,PSLONEM>[\r] { }
<INITIAL,PSLMULM,PSLONEM>. { return (VP_TEXT); }
%%

2
src/verilog.l
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@ -161,6 +161,7 @@ escid \\[^ \t\f\r\n]+
"casez" {yylval.fileline = CRELINE(); return yCASEZ;}
"default" {yylval.fileline = CRELINE(); return yDEFAULT;}
"defparam" {yylval.fileline = CRELINE(); return yDEFPARAM;}
"edge" {yylval.fileline = CRELINE(); return yaTIMINGSPEC;}
"else" {yylval.fileline = CRELINE(); return yELSE;}
"end" {yylval.fileline = CRELINE(); return yEND;}
"endcase" {yylval.fileline = CRELINE(); return yENDCASE;}
@ -217,7 +218,6 @@ escid \\[^ \t\f\r\n]+
"cmos" {yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}
"deassign" {yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}
"disable" {yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}
"edge" {yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}
"endprimitive" {yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}
"endtable" {yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}
"event" {yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}

2
src/verilog.y
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@ -31,7 +31,7 @@
#include "V3Global.h"
#define YYERROR_VERBOSE 1
#define YYMAXDEPTH 500
#define YYMAXDEPTH 1000
// Pick up new lexer
#define yylex V3Read::yylex