From 2c5a18336869017f53a8447eaa284923cde7626b Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Thu, 17 May 2007 16:15:24 +0000
Subject: [PATCH] Ignore ctrl-Zs in preprocessor

git-svn-id: file://localhost/svn/verilator/trunk/verilator@925 77ca24e4-aefa-0310-84f0-b9a241c72d87
---
 src/V3PreLex.l | 8 +++++++-
 src/verilog.l  | 2 +-
 src/verilog.y  | 2 +-
 3 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/src/V3PreLex.l b/src/V3PreLex.l
index 3e92a402a..ebf87c30c 100644
--- a/src/V3PreLex.l
+++ b/src/V3PreLex.l
@@ -58,12 +58,15 @@ static void pslMoreNeeded(bool flag) { V3PreLex::s_currentLexp->m_pslMoreNeeded
 %x ARGMODE
 %x INCMODE
 
+/* drop: Drop Ctrl-Z - can't pass thru or may EOF the output too soon */
+
 ws		[ \t\f\r]
 wsn		[ \t\f]
 crnl		[\r]*[\n]
 quote		[\"]
 backslash	[\\]
 symb		[a-zA-Z_][a-zA-Z0-9_$]*
+drop		[\032]
 psl		[p]sl
 
 	/**************************************************************/
@@ -113,6 +116,7 @@ psl		[p]sl
 	/* Reading definition */
 <DEFMODE>"/*"		{ yy_push_state(CMTMODE); yymore(); }
 <DEFMODE>"//"[^\n\r]*	{ return (VP_COMMENT);}
+<DEFMODE>{drop}		{ }
 <DEFMODE><<EOF>>	{ linenoInc(); yyerror("EOF (missing return?) in define value"); yyleng=0; yyterminate(); }
 <DEFMODE>{crnl}		{ linenoInc(); yy_pop_state(); yytext="\n"; yyleng=1; return (VP_DEFVALUE); }
 <DEFMODE>[\\]{crnl}	{ linenoInc(); appendDefValue("\n",1); } /* Include return so can maintain output line count */
@@ -123,6 +127,7 @@ psl		[p]sl
 	/* Define arguments */
 <ARGMODE>"/*"		{ yy_push_state(CMTMODE); yymore(); }
 <ARGMODE>"//"[^\n\r]*	{ return (VP_COMMENT);}
+<ARGMODE>{drop}		{ }
 <ARGMODE><<EOF>>	{ yyerror("EOF in define argument list\n"); yyleng = 0; yyterminate(); }
 <ARGMODE>{crnl}		{ linenoInc(); yytext="\n"; yyleng=1; return(VP_WHITE); }
 <ARGMODE>{quote}	{ yy_push_state(STRMODE); yymore(); }
@@ -179,8 +184,9 @@ psl		[p]sl
 	/* Generics */
 <INITIAL,PSLMULM>{crnl}		{ linenoInc(); yytext="\n"; yyleng=1; return(VP_WHITE); }
 <INITIAL,PSLMULM,PSLONEM>{symb}	{ return (VP_SYMBOL); }
-<INITIAL,PSLMULM,PSLONEM>[\r]	{ }
 <INITIAL,PSLMULM,PSLONEM>{wsn}+	{ return (VP_WHITE); }
+<INITIAL,PSLMULM,PSLONEM>{drop}	{ }
+<INITIAL,PSLMULM,PSLONEM>[\r]	{ }
 <INITIAL,PSLMULM,PSLONEM>.	{ return (VP_TEXT); }
 %%
 
diff --git a/src/verilog.l b/src/verilog.l
index 3f8cca1b3..90713d3c6 100644
--- a/src/verilog.l
+++ b/src/verilog.l
@@ -161,6 +161,7 @@ escid	\\[^ \t\f\r\n]+
   "casez"		{yylval.fileline = CRELINE(); return yCASEZ;}
   "default"		{yylval.fileline = CRELINE(); return yDEFAULT;}
   "defparam"		{yylval.fileline = CRELINE(); return yDEFPARAM;}
+  "edge"		{yylval.fileline = CRELINE(); return yaTIMINGSPEC;}
   "else"		{yylval.fileline = CRELINE(); return yELSE;}
   "end"			{yylval.fileline = CRELINE(); return yEND;}
   "endcase"		{yylval.fileline = CRELINE(); return yENDCASE;}
@@ -217,7 +218,6 @@ escid	\\[^ \t\f\r\n]+
   "cmos"		{yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}
   "deassign"		{yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}
   "disable"		{yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}
-  "edge"		{yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}
   "endprimitive"	{yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}
   "endtable"		{yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}
   "event"		{yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);}
diff --git a/src/verilog.y b/src/verilog.y
index d286e076f..4aa1e4c07 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -31,7 +31,7 @@
 #include "V3Global.h"
 
 #define YYERROR_VERBOSE 1
-#define YYMAXDEPTH 500
+#define YYMAXDEPTH 1000
 
 // Pick up new lexer
 #define yylex V3Read::yylex