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Fix latex warning & misc Commentary

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This commit is contained in:
Wilson Snyder 2018-05-13 19:21:08 -04:00
parent 51422e3ee8
commit 2c568603f6
3 changed files with 5 additions and 4 deletions
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1
MANIFEST.SKIP
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@ -17,6 +17,7 @@
/obj_dbg/
/obj_opt/
/obj_vlt/
/obj_vltmt/
/obj_dist/
/INCA_libs/
/cov_work/

4
bin/verilator
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@ -228,8 +228,8 @@ Verilator - Convert Verilog code to C++/SystemC
=head1 DESCRIPTION
Verilator converts synthesizable (not behavioral) Verilog code, plus some
Synthesis, SystemVerilog and a small subset of Verilog AMS assertions, into
Verilator converts synthesizable (generally not behavioral) Verilog code,
plus some Synthesis, SystemVerilog and a small subset of Verilog AMS into
C++ or SystemC code. It is not a complete simulator, but a compiler.
Verilator is invoked with parameters similar to GCC, Cadence

4
src/pod2latexfix
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@ -27,7 +27,7 @@ my $header = ("\\usepackage[left=1.7in,right=1.7in,top=1.3in,bottom=1.3in]{geome
);
foreach my $line (<STDIN>) {
$line =~ s/(\\begin{document})/${header}$1/;
$line =~ s/(\\tableofcontents)/\\begin{titlepage} \\maketitle \\end{titlepage}\n$1/;
$line =~ s/(\\begin\{document\})/${header}$1/;
$line =~ s/(\\tableofcontents)/\\begin\{titlepage\} \\maketitle \\end\{titlepage\}\n$1/;
print "$line";
}