From 2c568603f668c04cfb536e963928efe9cf9569e2 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Sun, 13 May 2018 19:21:08 -0400
Subject: [PATCH] Fix latex warning & misc Commentary

---
 MANIFEST.SKIP    | 1 +
 bin/verilator    | 4 ++--
 src/pod2latexfix | 4 ++--
 3 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/MANIFEST.SKIP b/MANIFEST.SKIP
index 4259ac3df..d1e23b9ff 100644
--- a/MANIFEST.SKIP
+++ b/MANIFEST.SKIP
@@ -17,6 +17,7 @@
 /obj_dbg/
 /obj_opt/
 /obj_vlt/
+/obj_vltmt/
 /obj_dist/
 /INCA_libs/
 /cov_work/
diff --git a/bin/verilator b/bin/verilator
index 5465f6265..9e5a0858e 100755
--- a/bin/verilator
+++ b/bin/verilator
@@ -228,8 +228,8 @@ Verilator - Convert Verilog code to C++/SystemC
 
 =head1 DESCRIPTION
 
-Verilator converts synthesizable (not behavioral) Verilog code, plus some
-Synthesis, SystemVerilog and a small subset of Verilog AMS assertions, into
+Verilator converts synthesizable (generally not behavioral) Verilog code,
+plus some Synthesis, SystemVerilog and a small subset of Verilog AMS into
 C++ or SystemC code.  It is not a complete simulator, but a compiler.
 
 Verilator is invoked with parameters similar to GCC, Cadence
diff --git a/src/pod2latexfix b/src/pod2latexfix
index 7c2121d31..0bf026e54 100755
--- a/src/pod2latexfix
+++ b/src/pod2latexfix
@@ -27,7 +27,7 @@ my $header = ("\\usepackage[left=1.7in,right=1.7in,top=1.3in,bottom=1.3in]{geome
 	      );
 
 foreach my $line (<STDIN>) {
-    $line =~ s/(\\begin{document})/${header}$1/;
-    $line =~ s/(\\tableofcontents)/\\begin{titlepage} \\maketitle \\end{titlepage}\n$1/;
+    $line =~ s/(\\begin\{document\})/${header}$1/;
+    $line =~ s/(\\tableofcontents)/\\begin\{titlepage\} \\maketitle \\end\{titlepage\}\n$1/;
     print "$line";
 }