Lesser license for verilated files

git-svn-id: file://localhost/svn/verilator/trunk/verilator@931 77ca24e4-aefa-0310-84f0-b9a241c72d87

bin/verilator

@@ -320,6 +320,12 @@ internal assertions, debugging messages, and intermediate form dump files.
 Rarely needed.  Enable internal debugging assertion checks, without
 changing debug verbosity.  Enabled automatically when --debug specified.
 
+=item --dump-tree
+
+Rarely needed.  Enable writing .tree debug files.  This is enabled with
+--debug, so "--debug --no-dump-tree" may be useful if the dump files are
+large and not desired.
+
 =item -E
 
 Preprocess the source code, but do not compile, as with 'gcc -E'.  Output
@@ -1870,6 +1876,25 @@ so your simulator shouldn't have to be -- and Verilator is closer to the
 synthesis interpretation, so this is a good thing for getting working
 silicon.
 
+=item May programs I create with Verilator remain under my own copyright?
+
+Yes, it's just like using GCC on your programs.  If you change Verilator
+itself, you must make the source code available under the GNU Public
+License.  However, the include and generated files use the GNU Lesser
+Public License, which means that files using them are NOT required to be released.
+
+You also have the option of using the Perl Artistic License, which again
+does not require you release your Verilog or generated code.
+
+=item Why is running Verilator so slow?
+
+Verilator needs more memory then the resulting simulator will require, as
+Verilator creates internally all of the state of the resulting simulator in
+order to optimize it.  If it takes more then a minute or so (and you're not
+using --debug), see if your machine is paging; most likely you need to run
+it on a machine with more memory.  Verilator is a full 64 bit application
+and may use more then 4GB, but about 1GB is the maximum typically needed.
+
 =item How do I generate waveforms (traces) in C++?
 
 See the next question for SystemC mode.

include/verilated.cpp

@@ -3,7 +3,7 @@
 //
 // Copyright 2003-2007 by Wilson Snyder. This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
-// General Public License or the Perl Artistic License.
+// Lesser General Public License or the Perl Artistic License.
 //
 // Verilator is distributed in the hope that it will be useful,
 // but WITHOUT ANY WARRANTY; without even the implied warranty of

include/verilated.h

@@ -3,7 +3,7 @@
 //
 // Copyright 2003-2007 by Wilson Snyder. This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
-// General Public License or the Perl Artistic License.
+// Lesser General Public License or the Perl Artistic License.
 //
 // Verilator is distributed in the hope that it will be useful,
 // but WITHOUT ANY WARRANTY; without even the implied warranty of

include/verilated.mk.in

@@ -4,7 +4,7 @@
 #
 # Copyright 2003-2007 by Wilson Snyder. This program is free software; you can
 # redistribute it and/or modify it under the terms of either the GNU
-# General Public License or the Perl Artistic License.
+# Lesser General Public License or the Perl Artistic License.
 ######################################################################
 
 PERL = @PERL@

include/verilated.v

@@ -7,7 +7,7 @@
 //
 // Copyright 2003-2007 by Wilson Snyder. This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
-// General Public License or the Perl Artistic License.
+// Lesser General Public License or the Perl Artistic License.
 //
 // This is distributed in the hope that it will be useful,
 // but WITHOUT ANY WARRANTY; without even the implied warranty of

include/verilatedos.h

@@ -3,7 +3,7 @@
 //
 // Copyright 2003-2007 by Wilson Snyder. This program is free software; you can
 // redistribute it and/or modify it under the terms of either the GNU
-// General Public License or the Perl Artistic License.
+// Lesser General Public License or the Perl Artistic License.
 //
 // Verilator is distributed in the hope that it will be useful,
 // but WITHOUT ANY WARRANTY; without even the implied warranty of

src/verilog.l

@@ -718,7 +718,7 @@ escid	\\[^ \t\f\r\n]+
 
 <V95,V01,V05,S05,PSL>{
   "`"[a-zA-Z_0-9]+	{ yyerrorf("Define or directive not defined: %s",yytext); }
-  "//"[^\n]+		{ }  /* throw away single line comments */
+  "//"[^\n]*		{ }  /* throw away single line comments */
   .			{yylval.fileline = CRELINE(); return yytext[0];}	/* return single char ops. */
 }