Version bump

git-svn-id: file://localhost/svn/verilator/trunk/verilator@928 77ca24e4-aefa-0310-84f0-b9a241c72d87

Changes

@@ -3,7 +3,7 @@ Revision history for Verilator
 The contributors that suggested a given feature are shown in [].  [by ...]
 indicates the contributor was also the author of the fix; Thanks!
 
-* Verilator 3.65**
+* Verilator 3.651 5/22/2007
 
 ***  Added verilator_profcfunc utility.  [Gene Weber]
 

bin/verilator

@@ -1434,6 +1434,14 @@ This section describes specific limitations for each language keyword.
 
 =over 4
 
+=item `__FILE__, `__LINE__, `begin_keywords, `begin_keywords, `begin_keywords,
+`begin_keywords, `begin_keywords, `define, `else, `elsif, `end_keywords,
+`endif, `error, `ifdef, `ifndef, `include, `line, `systemc_ctor,
+`systemc_dtor, `systemc_header, `systemc_imp_header,
+`systemc_implementation, `systemc_interface, `timescale, `undef, `verilog
+
+Fully supported.
+
 =item always, always_comb, always_ff, always_latch, and, assign, begin,
 buf, case, casex, casez, default, defparam, do-while, else, end, endcase,
 endfunction, endgenerate, endmodule, endspecify, endtask, final, for,
@@ -1453,8 +1461,9 @@ All specify blocks and timing checks are ignored.
 Verilator does not perform warning checking on uwires, it treats the uwire
 keyword as if it were the normal wire keyword.
 
-=item $bits, $countones, $finish, $isunknown, $onehot, $onehot0, $readmemb,
-$readmemh, $signed, $stop, $time, $unsigned
+=item $bits, $countones, $error, $fatal, $finish, $info, $isunknown,
+$onehot, $onehot0, $readmemb, $readmemh, $signed, $stop, $time, $unsigned,
+$warning.
 
 Generally supported.
 
@@ -2069,7 +2078,7 @@ Communications, Sun Microsystems, Nauticus Networks, and SiCortex.
 
 The people who have contributed code or other major functionality are Paul
 Wasson, Duane Galbi, and Wilson Snyder.  Major testers include Jeff Dutton,
-Ralf Karge and Wim Michiels.
+Ralf Karge, David Hewson, Wim Michiels, and Gene Weber.
 
 Some of the people who have provided ideas and feedback for Verilator
 include Hans Van Antwerpen, Jens Arm, David Black, Gregg Bouchard, Chris

bin/verilator_profcfunc

@@ -78,29 +78,78 @@ sub profcfunc {
     my %funcs;
 
     while (defined (my $line=$fh->getline())) {
-	if ($line =~ /^\s*([0-9.]+)\s+[0-9.]+\s+([0-9.]+)\s+([0-9.]+)\s+.*__PROF__([a-zA-Z_0-9]+)__([0-9]+)\(/) {
-	    my $fileline = sprintf("%s:%d", $4, $5);
-	    $funcs{$fileline}{pct} += $1;
-	    $funcs{$fileline}{sec} += $2;
-	    $funcs{$fileline}{calls} += $3;
+	if ($line =~ /^\s*([0-9.]+)\s+[0-9.]+\s+([0-9.]+)\s+([0-9.]+)\s+.*\s+(\S+)\s*$/) {
+	    my $pct=$1; my $sec=$2; my $calls=$3; my $func=$4;
+	    $funcs{$func}{pct} += $pct;
+	    $funcs{$func}{sec} += $sec;
+	    $funcs{$func}{calls} += $calls;
 	}
     }
     $fh->close;
 
+    # Find modules
+    my %verilated_mods;
+    foreach my $func (keys %funcs) {
+	if ($func =~ /(.*)::_eval\(.*__Syms.*\)$/) {
+	    $verilated_mods{$1} = qr/^$1/;
+	}
+    }
+
+    # Resort by Verilog name
+    my %vfuncs;
+    my %groups;
+    foreach my $func (keys %funcs) {
+	my $vfunc = $func;
+	my $design;
+	foreach my $vde (keys %verilated_mods) {
+	    if ($func =~ /$verilated_mods{$vde}/) {
+		$design=$vde;
+		last;
+	    }
+	}
+	if ($vfunc =~ /__PROF__([a-zA-Z_0-9]+)__([0-9]+)\(/) {
+	    $vfunc     = sprintf("VBlock    %s:%d", $1, $2);
+	    $groups{"Verilog Blocks under $design"} += $funcs{$func}{pct};
+	} else {
+	    if ($design) {
+		$vfunc = sprintf("VCommon   %s", $func);
+		$groups{"Common code under $design"} += $funcs{$func}{pct};
+	    } else {
+		$vfunc = sprintf("C++       %s", $func);
+		$groups{'C++'} += $funcs{$func}{pct};
+	    }
+	}
+	$vfuncs{$vfunc} = $funcs{$func};
+    }
+
+    print("Overall summary:\n");
+    print("  % time\n");
+    foreach (sort (keys %groups)) {
+	printf("  %6.2f  In all %s\n", $groups{$_}, $_);
+    }
+    print("\n");
+
+
+    print("Verilog code profile:\n");
+    print("   These are split into three categories:\n");
+    print("      C++:     Time in non-Verilated C++ code\n");
+    print("      VBlock:  Time attributable to a block in a Verilog file and line\n");
+    print("      VCommon: Time in a Verilated module, due to all parts of the design\n");
+    print("\n");
 
-    print("Verilog code profile\n");
     print("  %   cumulative   self              \n");
-    print(" time   seconds   seconds    calls   filename and line number\n");
+    print(" time   seconds   seconds    calls   type      filename and line number\n");
 
     my $cume = 0;
-    foreach my $fileline (sort {$funcs{$b}{sec} <=> $funcs{$a}{sec}
-				|| $a cmp $b}
-			  (keys %funcs)) {
-	$cume += $funcs{$fileline}{sec};
-	printf +("%6.2f %9.2f %8.2f %8d   %s\n", $funcs{$fileline}{pct},
-		 $cume, $funcs{$fileline}{sec},
-		 $funcs{$fileline}{calls},
-		 $fileline);
+    foreach my $func (sort {$vfuncs{$b}{sec} <=> $vfuncs{$a}{sec}
+			    || $a cmp $b}
+		      (keys %vfuncs)) {
+	$cume += $vfuncs{$func}{sec};
+	printf +("%6.2f %9.2f %8.2f %8d   %s\n",
+		 $vfuncs{$func}{pct},
+		 $cume, $vfuncs{$func}{sec},
+		 $vfuncs{$func}{calls},
+		 $func);
     }
 }
 

src/V3Ast.h

@@ -999,7 +999,7 @@ private:
     AstNodeFTask*	m_taskp;	// [AfterLink] Pointer to task referenced
     string		m_name;		// Name of variable
     string		m_dotted;	// Dotted part of scope to task or ""
-    string		m_inlinedDots;	// Dotted hiearchy flattened out
+    string		m_inlinedDots;	// Dotted hierarchy flattened out
 public:
     AstNodeFTaskRef(FileLine* fl, AstNode* namep, AstNode* pinsp)
 	:AstNode(fl)

src/V3AstNodes.h

@@ -421,7 +421,7 @@ struct AstScope : public AstNode {
 private:
     string	m_name;		// Name
     AstScope*	m_aboveScopep;	// Scope above this one in the hierarchy (NULL if top)
-    AstCell*	m_aboveCellp;	// Cell above this in the hiearchy (NULL if top)
+    AstCell*	m_aboveCellp;	// Cell above this in the hierarchy (NULL if top)
     AstModule*	m_modp;		// Module scope corresponds to
 public:
     AstScope(FileLine* fl, AstModule* modp, const string& name,
@@ -540,7 +540,7 @@ struct AstVarXRef : public AstNodeVarRef {
     // Includes pin on a cell, as part of a ASSIGN statement to connect I/Os until AstScope
 private:
     string	m_dotted;	// Scope name to connected to
-    string	m_inlinedDots;	// Dotted hiearchy flattened out
+    string	m_inlinedDots;	// Dotted hierarchy flattened out
 public:
     AstVarXRef(FileLine* fl, const string& name, const string& dotted, bool lvalue)
 	:AstNodeVarRef(fl, name, NULL, lvalue)

src/V3LinkDot.cpp

@@ -21,7 +21,7 @@
 // LinkDot TRANSFORMATIONS:
 //	Top-down traversal
 //	    Cells:
-//		Make graph of cell hiearchy
+//		Make graph of cell hierarchy
 //	    Var/Funcs's:
 //		Collect all names into symtable under appropriate cell
 //	Top-down traversal
@@ -180,7 +180,7 @@ private:
     // TYPES
     typedef std::multimap<string,LinkDotCellVertex*> NameScopeMap;
     // MEMBERS
-    LinkDotGraph	m_graph;		// Graph of hiearchy
+    LinkDotGraph	m_graph;		// Graph of hierarchy
     NameScopeMap	m_nameScopeMap;		// Hash of scope referenced by non-pretty textual name
     bool		m_forPrearray;		// Compress cell__[array] refs
     bool		m_forScopeCreation;	// Remove VarXRefs for V3Scope
@@ -277,7 +277,7 @@ private:
 public:
     LinkDotBaseVertex* findDotted(LinkDotBaseVertex* cellVxp, const string& dotname,
 				  string& baddot, LinkDotBaseVertex*& okVxp) {
-	// Given a dotted hiearchy name, return where in scope it is
+	// Given a dotted hierarchy name, return where in scope it is
 	// Note when dotname=="" we just fall through and return cellVxp
 	UINFO(8,"    dottedFind "<<dotname<<endl);
 	bool firstId = true;
@@ -520,8 +520,8 @@ private:
     virtual void visit(AstScope* nodep, AstNUser*) {
 	UINFO(8,"  SCOPE "<<nodep<<endl);
 	if (!m_statep->forScopeCreation()) v3fatalSrc("Scopes should only exist right after V3Scope");
-	// Using the CELL names, we created all hiearchy.  We now need to match this Scope
-	// up with the hiearchy created by the CELL names.
+	// Using the CELL names, we created all hierarchy.  We now need to match this Scope
+	// up with the hierarchy created by the CELL names.
 	m_cellVxp = m_statep->findScope(nodep);
 	nodep->iterateChildren(*this);
 	m_cellVxp = NULL;
@@ -610,7 +610,7 @@ private:
 	UINFO(8,"     "<<nodep<<endl);
 	if (!m_cellVxp) {
 	    UINFO(9,"Dead module for "<<nodep<<endl);
-	    nodep->varp(NULL);  // Module that is not in hiearchy.  We'll be dead code eliminating it later.
+	    nodep->varp(NULL);  // Module that is not in hierarchy.  We'll be dead code eliminating it later.
 	} else {
 	    string baddot;
 	    LinkDotBaseVertex* okVxp;
@@ -657,7 +657,7 @@ private:
 	UINFO(8,"     "<<nodep<<endl);
 	if (!m_cellVxp) {
 	    UINFO(9,"Dead module for "<<nodep<<endl);
-	    nodep->taskp(NULL);  // Module that is not in hiearchy.  We'll be dead code eliminating it later.
+	    nodep->taskp(NULL);  // Module that is not in hierarchy.  We'll be dead code eliminating it later.
 	} else {
 	    string baddot;
 	    LinkDotBaseVertex* okVxp;

src/config_build.h.in

@@ -24,7 +24,7 @@
 //**********************************************************************
 //**** Version and host name
 
-#define DTVERSION	"Verilator 3.650 4/20/2007"
+#define DTVERSION	"Verilator 3.651 4/20/2007"
 
 //**********************************************************************
 //**** Functions