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Tests: Fix buggy size test.
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@ -29,6 +29,9 @@ interface simple_bus #(AWIDTH = 8, DWIDTH = 8)
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output req, addr,
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output data);
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initial begin
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if (DWIDTH != 16) $stop;
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end
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endinterface: simple_bus
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module mem(interface a);
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@ -36,7 +39,7 @@ module mem(interface a);
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always @(posedge a.clk)
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a.gnt <= a.req & avail;
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initial begin
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if ($bits(a.data != 16)) $stop;
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if ($bits(a.data) != 16) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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