From 2a43410fa6062d62d464a9bf762fadaf9c9876a3 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Mon, 26 Nov 2018 18:22:20 -0500
Subject: [PATCH] Tests: Fix buggy size test.

---
 test_regress/t/t_interface_param2.v | 15 +++++++++------
 1 file changed, 9 insertions(+), 6 deletions(-)

diff --git a/test_regress/t/t_interface_param2.v b/test_regress/t/t_interface_param2.v
index 87cb46ee6..0b2afd5a0 100644
--- a/test_regress/t/t_interface_param2.v
+++ b/test_regress/t/t_interface_param2.v
@@ -15,20 +15,23 @@ module t (input clk);
 endmodule
 
 interface simple_bus #(AWIDTH = 8, DWIDTH = 8)
-   (input logic clk); // Define the interface
+   (input logic clk);  // Define the interface
 
    logic req, gnt;
    logic [AWIDTH-1:0] addr;
    logic [DWIDTH-1:0] data;
 
    modport slave( input req, addr, clk,
-		  output gnt,
-		  input  data);
+                  output gnt,
+                  input  data);
 
    modport master(input gnt, clk,
-		  output req, addr,
-		  output data);
+                  output req, addr,
+                  output data);
 
+   initial begin
+      if (DWIDTH != 16) $stop;
+   end
 endinterface: simple_bus
 
 module mem(interface a);
@@ -36,7 +39,7 @@ module mem(interface a);
    always @(posedge a.clk)
      a.gnt <= a.req & avail;
    initial begin
-      if ($bits(a.data != 16)) $stop;
+      if ($bits(a.data) != 16) $stop;
       $write("*-* All Finished *-*\n");
       $finish;
    end