From 2284ada72304b83587b774510c65d2fd31f281b5 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Sat, 30 Nov 2024 18:56:36 -0500
Subject: [PATCH] Tests: Interface-to-wire (#5649 test partial)

---
 test_regress/t/t_iface_wire_bad.out       |  5 +++++
 test_regress/t/t_iface_wire_bad.py        | 16 ++++++++++++++++
 test_regress/t/t_iface_wire_bad.v         | 17 +++++++++++++++++
 test_regress/t/t_iface_wire_bad_param.out |  5 +++++
 test_regress/t/t_iface_wire_bad_param.py  | 16 ++++++++++++++++
 test_regress/t/t_iface_wire_bad_param.v   | 17 +++++++++++++++++
 6 files changed, 76 insertions(+)
 create mode 100644 test_regress/t/t_iface_wire_bad.out
 create mode 100755 test_regress/t/t_iface_wire_bad.py
 create mode 100644 test_regress/t/t_iface_wire_bad.v
 create mode 100644 test_regress/t/t_iface_wire_bad_param.out
 create mode 100755 test_regress/t/t_iface_wire_bad_param.py
 create mode 100644 test_regress/t/t_iface_wire_bad_param.v

diff --git a/test_regress/t/t_iface_wire_bad.out b/test_regress/t/t_iface_wire_bad.out
new file mode 100644
index 000000000..f0d4767da
--- /dev/null
+++ b/test_regress/t/t_iface_wire_bad.out
@@ -0,0 +1,5 @@
+%Error: t/t_iface_wire_bad.v:16:20: Operator ASSIGNW expected non-interface on Assign RHS but 'a__Viftop' is an interface.
+                                  : ... note: In instance 't'
+   16 |    wire wbad = sub.a;
+      |                    ^
+%Error: Exiting due to
diff --git a/test_regress/t/t_iface_wire_bad.py b/test_regress/t/t_iface_wire_bad.py
new file mode 100755
index 000000000..31228c9a7
--- /dev/null
+++ b/test_regress/t/t_iface_wire_bad.py
@@ -0,0 +1,16 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('linter')
+
+test.lint(fails=True, expect_filename=test.golden_filename)
+
+test.passes()
diff --git a/test_regress/t/t_iface_wire_bad.v b/test_regress/t/t_iface_wire_bad.v
new file mode 100644
index 000000000..5a01c4e64
--- /dev/null
+++ b/test_regress/t/t_iface_wire_bad.v
@@ -0,0 +1,17 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2024 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+interface Ifc;
+endinterface
+
+module Sub;
+   Ifc a();
+endmodule
+
+module t;
+   Sub sub();
+   wire wbad = sub.a;
+endmodule
diff --git a/test_regress/t/t_iface_wire_bad_param.out b/test_regress/t/t_iface_wire_bad_param.out
new file mode 100644
index 000000000..ff54bf85d
--- /dev/null
+++ b/test_regress/t/t_iface_wire_bad_param.out
@@ -0,0 +1,5 @@
+%Error: Internal Error: t/t_iface_wire_bad_param.v:16:20: ../V3Broken.cpp:#: Broken link in node (or something without maybePointedTo): 'm_varp && !m_varp->brokeExists()' @ ./V3Ast__gen_impl.h:#
+                                                        : ... note: In instance 't'
+   16 |    wire wbad = sub.a;
+      |                    ^
+                        ... See the manual at https://verilator.org/verilator_doc.html for more assistance.
diff --git a/test_regress/t/t_iface_wire_bad_param.py b/test_regress/t/t_iface_wire_bad_param.py
new file mode 100755
index 000000000..31228c9a7
--- /dev/null
+++ b/test_regress/t/t_iface_wire_bad_param.py
@@ -0,0 +1,16 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('linter')
+
+test.lint(fails=True, expect_filename=test.golden_filename)
+
+test.passes()
diff --git a/test_regress/t/t_iface_wire_bad_param.v b/test_regress/t/t_iface_wire_bad_param.v
new file mode 100644
index 000000000..d814123ea
--- /dev/null
+++ b/test_regress/t/t_iface_wire_bad_param.v
@@ -0,0 +1,17 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2024 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+interface Ifc;
+endinterface
+
+module Sub #(parameter P);
+   Ifc a();
+endmodule
+
+module t;
+   Sub #(0) sub();
+   wire wbad = sub.a;
+endmodule