From 2267db093fc194c41fa11a2b78cb56814c58f208 Mon Sep 17 00:00:00 2001
From: Ryszard Rozak <rrozak@antmicro.com>
Date: Thu, 11 May 2023 00:34:29 +0200
Subject: [PATCH] Fix hashes of instances of parameterized classes (#4182)

---
 src/V3Hasher.cpp                        |  2 +-
 test_regress/t/t_class_param_typedef.pl | 21 +++++++++++
 test_regress/t/t_class_param_typedef.v  | 47 +++++++++++++++++++++++++
 3 files changed, 69 insertions(+), 1 deletion(-)
 create mode 100755 test_regress/t/t_class_param_typedef.pl
 create mode 100644 test_regress/t/t_class_param_typedef.v

diff --git a/src/V3Hasher.cpp b/src/V3Hasher.cpp
index c68f1167e..432f62b17 100644
--- a/src/V3Hasher.cpp
+++ b/src/V3Hasher.cpp
@@ -307,7 +307,7 @@ private:
     }
     void visit(AstNodeModule* nodep) override {
         m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, false, [=]() {  //
-            m_hash += nodep->origName();
+            m_hash += nodep->name();
         });
     }
     void visit(AstNodePreSel* nodep) override {
diff --git a/test_regress/t/t_class_param_typedef.pl b/test_regress/t/t_class_param_typedef.pl
new file mode 100755
index 000000000..1aa73f80a
--- /dev/null
+++ b/test_regress/t/t_class_param_typedef.pl
@@ -0,0 +1,21 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2022 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_class_param_typedef.v b/test_regress/t/t_class_param_typedef.v
new file mode 100644
index 000000000..0218b205a
--- /dev/null
+++ b/test_regress/t/t_class_param_typedef.v
@@ -0,0 +1,47 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2023 by Antmicro Ltd.
+// SPDX-License-Identifier: CC0-1.0
+
+class Foo #(type T=int);
+   typedef Foo#(T) this_type;
+   function int get_x;
+      return T::get_s_x();
+   endfunction
+endclass
+
+class Bar #(type S=int);
+   typedef Bar #(S) this_type;
+   typedef Foo#(this_type) foo_type;
+   function int get_x;
+      foo_type f = new;
+      return f.get_x();
+   endfunction
+   static function int get_s_x;
+      return S::x;
+   endfunction
+endclass
+
+class Cls1;
+   static int x = 1;
+   typedef Bar#(Cls1) type_id;
+endclass
+
+class Cls2;
+   static int x = 2;
+   typedef Bar#(Cls2) type_id;
+endclass
+
+module t;
+   initial begin
+      Cls1::type_id bar1 = new;
+      Cls2::type_id bar2 = new;
+
+      if (bar1.get_x() != 1) $stop;
+      if (bar2.get_x() != 2) $stop;
+
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule