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Fix empty generate region, bug422.

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This commit is contained in:
Wilson Snyder 2011-11-28 07:49:36 -05:00
parent 06b796c6bd
commit 20189f5191
2 changed files with 4 additions and 0 deletions
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1
src/verilog.y
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@ -1375,6 +1375,7 @@ non_port_module_item<nodep>: // ==IEEE: non_port_module_item
generate_region<nodep>: // ==IEEE: generate_region
yGENERATE genTopBlock yENDGENERATE { $$ = new AstGenerate($1, $2); }
| yGENERATE yENDGENERATE { $$ = NULL; }
;
module_or_generate_item<nodep>: // ==IEEE: module_or_generate_item

3
test_regress/t/t_gen_for.v
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@ -93,6 +93,9 @@ module paramed (/*AUTOARG*/
for (i=0; i<3; i=i+1) begin end
endgenerate
generate
endgenerate
generate
if (MODE==0) begin
// Flip bitorder, direct assign method