From 20189f519176b97b0940f0c08028e05b69c68615 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Mon, 28 Nov 2011 07:49:36 -0500
Subject: [PATCH] Fix empty generate region, bug422.

---
 src/verilog.y              | 1 +
 test_regress/t/t_gen_for.v | 3 +++
 2 files changed, 4 insertions(+)

diff --git a/src/verilog.y b/src/verilog.y
index 802f9a6fe..58c28f93e 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -1375,6 +1375,7 @@ non_port_module_item<nodep>:	// ==IEEE: non_port_module_item
 
 generate_region<nodep>:		// ==IEEE: generate_region
 		yGENERATE genTopBlock yENDGENERATE	{ $$ = new AstGenerate($1, $2); }
+	|	yGENERATE yENDGENERATE			{ $$ = NULL; }
 	;
 
 module_or_generate_item<nodep>:	// ==IEEE: module_or_generate_item
diff --git a/test_regress/t/t_gen_for.v b/test_regress/t/t_gen_for.v
index 174b4b9a2..ad6d44527 100644
--- a/test_regress/t/t_gen_for.v
+++ b/test_regress/t/t_gen_for.v
@@ -93,6 +93,9 @@ module paramed (/*AUTOARG*/
       for (i=0; i<3; i=i+1) begin end
    endgenerate
 
+   generate
+   endgenerate
+
    generate
       if (MODE==0) begin
 	 // Flip bitorder, direct assign method