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Tests: Rename some tests

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This commit is contained in:
Wilson Snyder 2022-09-27 18:42:03 -04:00
parent 1b18eee5dc
commit 1b1907af49
5 changed files with 6 additions and 0 deletions
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test_regress/t/t_write_format_bug.out → test_regress/t/t_display_concat2.out
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test_regress/t/t_write_format_bug.pl → test_regress/t/t_display_concat2.pl
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test_regress/t/t_write_format_bug.v → test_regress/t/t_display_concat2.v
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test_regress/t/t_void_queue_ops.pl → test_regress/t/t_queue_void_ops.pl
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test_regress/t/t_void_queue_ops.v → test_regress/t/t_queue_void_ops.v
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@ -1,3 +1,9 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2022 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t module t
(/*AUTOARG*/ (/*AUTOARG*/
// Inputs // Inputs