From 1b1907af4995ee5ac0212fc66ccccf72ed4b47c3 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Tue, 27 Sep 2022 18:42:03 -0400 Subject: [PATCH] Tests: Rename some tests --- .../t/{t_write_format_bug.out => t_display_concat2.out} | 0 .../t/{t_write_format_bug.pl => t_display_concat2.pl} | 0 .../t/{t_write_format_bug.v => t_display_concat2.v} | 0 test_regress/t/{t_void_queue_ops.pl => t_queue_void_ops.pl} | 0 test_regress/t/{t_void_queue_ops.v => t_queue_void_ops.v} | 6 ++++++ 5 files changed, 6 insertions(+) rename test_regress/t/{t_write_format_bug.out => t_display_concat2.out} (100%) rename test_regress/t/{t_write_format_bug.pl => t_display_concat2.pl} (100%) rename test_regress/t/{t_write_format_bug.v => t_display_concat2.v} (100%) rename test_regress/t/{t_void_queue_ops.pl => t_queue_void_ops.pl} (100%) rename test_regress/t/{t_void_queue_ops.v => t_queue_void_ops.v} (96%) diff --git a/test_regress/t/t_write_format_bug.out b/test_regress/t/t_display_concat2.out similarity index 100% rename from test_regress/t/t_write_format_bug.out rename to test_regress/t/t_display_concat2.out diff --git a/test_regress/t/t_write_format_bug.pl b/test_regress/t/t_display_concat2.pl similarity index 100% rename from test_regress/t/t_write_format_bug.pl rename to test_regress/t/t_display_concat2.pl diff --git a/test_regress/t/t_write_format_bug.v b/test_regress/t/t_display_concat2.v similarity index 100% rename from test_regress/t/t_write_format_bug.v rename to test_regress/t/t_display_concat2.v diff --git a/test_regress/t/t_void_queue_ops.pl b/test_regress/t/t_queue_void_ops.pl similarity index 100% rename from test_regress/t/t_void_queue_ops.pl rename to test_regress/t/t_queue_void_ops.pl diff --git a/test_regress/t/t_void_queue_ops.v b/test_regress/t/t_queue_void_ops.v similarity index 96% rename from test_regress/t/t_void_queue_ops.v rename to test_regress/t/t_queue_void_ops.v index f618cb876..b3363177c 100644 --- a/test_regress/t/t_void_queue_ops.v +++ b/test_regress/t/t_queue_void_ops.v @@ -1,3 +1,9 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2022 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + module t (/*AUTOARG*/ // Inputs