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Change --main and --binary to use a TOP hierarchy name of "" (#5482).

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This commit is contained in:
Wilson Snyder 2024-09-22 23:03:51 -04:00
parent 670b7c5243
commit 0aa8356eca
13 changed files with 73 additions and 78 deletions
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1
Changes
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@ -19,6 +19,7 @@ Verilator 5.029 devel
* Change .vlt config files to be read before .v files (#5185). [David Moberg] * Change .vlt config files to be read before .v files (#5185). [David Moberg]
* Change to use maximum for cover point aggregation (#5402). [Andrew Nolte] * Change to use maximum for cover point aggregation (#5402). [Andrew Nolte]
* Change `--main` and `--binary` to use a TOP hierarchy name of "" (#5482).
* Support IEEE-compliant intra-assign delays (#3711) (#5441). [Krzysztof Bieganski, Antmicro Ltd.] * Support IEEE-compliant intra-assign delays (#3711) (#5441). [Krzysztof Bieganski, Antmicro Ltd.]
* Support unconstrained randomization for unions (#5395) (#5396). [Yilou Wang] * Support unconstrained randomization for unions (#5395) (#5396). [Yilou Wang]
* Support basic constrained queue randomization (#5413). [Arkadiusz Kozdra, Antmicro Ltd.] * Support basic constrained queue randomization (#5413). [Arkadiusz Kozdra, Antmicro Ltd.]

7
src/V3EmitCMain.cpp
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@ -52,10 +52,7 @@ private:
// Optional main top name argument, with empty string replacement // Optional main top name argument, with empty string replacement
string topArg; string topArg;
string topName = v3Global.opt.mainTopName(); string topName = v3Global.opt.mainTopName();
if (!topName.empty()) { if (topName == "-") topName = "";
if (topName == "-") topName = "";
topArg = ", \"" + topName + "\"";
}
// Heavily commented output, as users are likely to look at or copy this code // Heavily commented output, as users are likely to look at or copy this code
ofp()->putsHeader(); ofp()->putsHeader();
@ -77,7 +74,7 @@ private:
puts("// Construct the Verilated model, from Vtop.h generated from Verilating\n"); puts("// Construct the Verilated model, from Vtop.h generated from Verilating\n");
puts("const std::unique_ptr<" + topClassName() + "> topp{new " + topClassName() puts("const std::unique_ptr<" + topClassName() + "> topp{new " + topClassName()
+ "{contextp.get()" + topArg + "}};\n"); + "{contextp.get(), \"" + topName + "\"}};\n");
puts("\n"); puts("\n");
puts("// Simulate until $finish\n"); puts("// Simulate until $finish\n");

2
test_regress/t/t_cover_main.out
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@ -1,2 +1,2 @@
# SystemC::Coverage-3 # SystemC::Coverage-3
C 'ft/t_cover_main.vl9n4pagev_line/toblockS9-11hTOP.t' 1 C 'ft/t_cover_main.vl9n4pagev_line/toblockS9-11h.t' 1

44
test_regress/t/t_timing_osc.out
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@ -1,27 +1,27 @@
$version Generated by VerilatedVcd $end $version Generated by VerilatedVcd $end
$timescale 1fs $end $timescale 1fs $end
$scope module TOP $end $scope module $rootio $end
$scope module tb_osc $end $upscope $end
$var wire 1 # dco_out $end $scope module tb_osc $end
$scope module dco $end $var wire 1 # dco_out $end
$var real 64 ' coarse_cw $end $scope module dco $end
$var real 64 ' medium_cw $end $var real 64 ' coarse_cw $end
$var real 64 ) fine_cw $end $var real 64 ' medium_cw $end
$var wire 1 # rf_out $end $var real 64 ) fine_cw $end
$var real 64 + coarse_ofst $end $var wire 1 # rf_out $end
$var real 64 - coarse_res $end $var real 64 + coarse_ofst $end
$var real 64 / medium_ofst $end $var real 64 - coarse_res $end
$var real 64 1 medium_res $end $var real 64 / medium_ofst $end
$var real 64 3 fine_ofst $end $var real 64 1 medium_res $end
$var real 64 5 fine_res $end $var real 64 3 fine_ofst $end
$var real 64 7 coarse_delay $end $var real 64 5 fine_res $end
$var real 64 9 medium_delay $end $var real 64 7 coarse_delay $end
$var real 64 ; fine_delay $end $var real 64 9 medium_delay $end
$var real 64 = jitter $end $var real 64 ; fine_delay $end
$var wire 1 $ coarse_out $end $var real 64 = jitter $end
$var wire 1 % medium_out $end $var wire 1 $ coarse_out $end
$var wire 1 & fine_out $end $var wire 1 % medium_out $end
$upscope $end $var wire 1 & fine_out $end
$upscope $end $upscope $end
$upscope $end $upscope $end
$enddefinitions $end $enddefinitions $end

6
test_regress/t/t_timing_timescale.out
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@ -20,7 +20,7 @@
[9e-06] clkb is 1 [9e-06] clkb is 1
[9.5e-06] clkb is 0 [9.5e-06] clkb is 0
[1e-05] clkb is 1 [1e-05] clkb is 1
[1e-05] Finishing (TOP.t.bot) [1e-05] Finishing (t.bot)
*-* All Finished *-* *-* All Finished *-*
[10500] final (TOP.t) [10500] final (t)
[1.05e-05] final (TOP.t.bot) count was 21 [1.05e-05] final (t.bot) count was 21

24
test_regress/t/t_timing_trace.out
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@ -1,17 +1,17 @@
$version Generated by VerilatedVcd $end $version Generated by VerilatedVcd $end
$timescale 1ps $end $timescale 1ps $end
$scope module TOP $end $scope module $rootio $end
$scope module t $end $upscope $end
$var wire 32 * CLK_PERIOD [31:0] $end $scope module t $end
$var wire 32 + CLK_HALF_PERIOD [31:0] $end $var wire 32 * CLK_PERIOD [31:0] $end
$var wire 1 # rst $end $var wire 32 + CLK_HALF_PERIOD [31:0] $end
$var wire 1 ( clk $end $var wire 1 # rst $end
$var wire 1 $ a $end $var wire 1 ( clk $end
$var wire 1 ) b $end $var wire 1 $ a $end
$var wire 1 % c $end $var wire 1 ) b $end
$var wire 1 & d $end $var wire 1 % c $end
$var event 1 ' ev $end $var wire 1 & d $end
$upscope $end $var event 1 ' ev $end
$upscope $end $upscope $end
$enddefinitions $end $enddefinitions $end

6
test_regress/t/t_timing_trace_fst.out
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@ -1,5 +1,5 @@
$date $date
Sun Nov 5 12:08:16 2023 Sun Sep 22 22:53:52 2024
$end $end
$version $version
@ -8,7 +8,8 @@ $end
$timescale $timescale
1ps 1ps
$end $end
$scope module TOP $end $scope module $rootio $end
$upscope $end
$scope module t $end $scope module t $end
$var parameter 32 ! CLK_PERIOD [31:0] $end $var parameter 32 ! CLK_PERIOD [31:0] $end
$var parameter 32 " CLK_HALF_PERIOD [31:0] $end $var parameter 32 " CLK_HALF_PERIOD [31:0] $end
@ -20,7 +21,6 @@ $var logic 1 ' c $end
$var logic 1 ( d $end $var logic 1 ( d $end
$var event 1 ) ev $end $var event 1 ) ev $end
$upscope $end $upscope $end
$upscope $end
$enddefinitions $end $enddefinitions $end
#0 #0
$dumpvars $dumpvars

10
test_regress/t/t_trace_binary.out
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@ -1,11 +1,9 @@
$version Generated by VerilatedVcd $end $version Generated by VerilatedVcd $end
$date Sun Oct 9 14:08:37 2022 $end
$timescale 1ps $end $timescale 1ps $end
$scope module $rootio $end
$scope module TOP $end $upscope $end
$scope module t $end $scope module t $end
$var wire 32 # sig [31:0] $end $var wire 32 # sig [31:0] $end
$upscope $end
$upscope $end $upscope $end
$enddefinitions $end $enddefinitions $end

8
test_regress/t/t_trace_class.out
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@ -1,9 +1,9 @@
$version Generated by VerilatedVcd $end $version Generated by VerilatedVcd $end
$timescale 1ps $end $timescale 1ps $end
$scope module TOP $end $scope module $rootio $end
$scope module $unit::Cls__P0__Vclpkg $end $upscope $end
$var wire 32 # PARAM [31:0] $end $scope module $unit::Cls__P0__Vclpkg $end
$upscope $end $var wire 32 # PARAM [31:0] $end
$upscope $end $upscope $end
$enddefinitions $end $enddefinitions $end

14
test_regress/t/t_trace_event.out
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@ -1,12 +1,12 @@
$version Generated by VerilatedVcd $end $version Generated by VerilatedVcd $end
$timescale 1ps $end $timescale 1ps $end
$scope module TOP $end $scope module $rootio $end
$scope module t $end $upscope $end
$var event 1 # ev_test $end $scope module t $end
$var wire 32 $ i [31:0] $end $var event 1 # ev_test $end
$var wire 1 % toggle $end $var wire 32 $ i [31:0] $end
$var wire 1 & clk $end $var wire 1 % toggle $end
$upscope $end $var wire 1 & clk $end
$upscope $end $upscope $end
$enddefinitions $end $enddefinitions $end

6
test_regress/t/t_trace_event_fst.out
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@ -1,5 +1,5 @@
$date $date
Tue Sep 10 16:34:40 2024 Sun Sep 22 22:54:12 2024
$end $end
$version $version
@ -8,14 +8,14 @@ $end
$timescale $timescale
1ps 1ps
$end $end
$scope module TOP $end $scope module $rootio $end
$upscope $end
$scope module t $end $scope module t $end
$var event 1 ! ev_test $end $var event 1 ! ev_test $end
$var int 32 " i [31:0] $end $var int 32 " i [31:0] $end
$var bit 1 # toggle $end $var bit 1 # toggle $end
$var bit 1 $ clk $end $var bit 1 $ clk $end
$upscope $end $upscope $end
$upscope $end
$enddefinitions $end $enddefinitions $end
#0 #0
$dumpvars $dumpvars

10
test_regress/t/t_trace_param_override.out
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@ -1,10 +1,10 @@
$version Generated by VerilatedVcd $end $version Generated by VerilatedVcd $end
$timescale 1ps $end $timescale 1ps $end
$scope module TOP $end $scope module $rootio $end
$scope module t $end $upscope $end
$var wire 32 # POVERRODE [31:0] $end $scope module t $end
$var wire 32 $ PORIG [31:0] $end $var wire 32 # POVERRODE [31:0] $end
$upscope $end $var wire 32 $ PORIG [31:0] $end
$upscope $end $upscope $end
$enddefinitions $end $enddefinitions $end

13
test_regress/t/t_trace_timing1.out
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@ -1,12 +1,11 @@
$version Generated by VerilatedVcd $end $version Generated by VerilatedVcd $end
$timescale 1ps $end $timescale 1ps $end
$scope module $rootio $end
$scope module TOP $end $upscope $end
$scope module t $end $scope module t $end
$var wire 32 % CLOCK_CYCLE [31:0] $end $var wire 32 % CLOCK_CYCLE [31:0] $end
$var wire 1 # rst $end $var wire 1 # rst $end
$var wire 1 $ clk $end $var wire 1 $ clk $end
$upscope $end
$upscope $end $upscope $end
$enddefinitions $end $enddefinitions $end