From 0aa8356ecad840d7e1cd82ff9c41e2e9c6b99efb Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sun, 22 Sep 2024 23:03:51 -0400 Subject: [PATCH] Change `--main` and `--binary` to use a TOP hierarchy name of "" (#5482). --- Changes | 1 + src/V3EmitCMain.cpp | 7 ++-- test_regress/t/t_cover_main.out | 2 +- test_regress/t/t_timing_osc.out | 44 +++++++++++------------ test_regress/t/t_timing_timescale.out | 6 ++-- test_regress/t/t_timing_trace.out | 24 ++++++------- test_regress/t/t_timing_trace_fst.out | 6 ++-- test_regress/t/t_trace_binary.out | 10 +++--- test_regress/t/t_trace_class.out | 8 ++--- test_regress/t/t_trace_event.out | 14 ++++---- test_regress/t/t_trace_event_fst.out | 6 ++-- test_regress/t/t_trace_param_override.out | 10 +++--- test_regress/t/t_trace_timing1.out | 13 ++++--- 13 files changed, 73 insertions(+), 78 deletions(-) diff --git a/Changes b/Changes index 0b351d5ab..5cadc4502 100644 --- a/Changes +++ b/Changes @@ -19,6 +19,7 @@ Verilator 5.029 devel * Change .vlt config files to be read before .v files (#5185). [David Moberg] * Change to use maximum for cover point aggregation (#5402). [Andrew Nolte] +* Change `--main` and `--binary` to use a TOP hierarchy name of "" (#5482). * Support IEEE-compliant intra-assign delays (#3711) (#5441). [Krzysztof Bieganski, Antmicro Ltd.] * Support unconstrained randomization for unions (#5395) (#5396). [Yilou Wang] * Support basic constrained queue randomization (#5413). [Arkadiusz Kozdra, Antmicro Ltd.] diff --git a/src/V3EmitCMain.cpp b/src/V3EmitCMain.cpp index 6112f2f2c..75789c798 100644 --- a/src/V3EmitCMain.cpp +++ b/src/V3EmitCMain.cpp @@ -52,10 +52,7 @@ private: // Optional main top name argument, with empty string replacement string topArg; string topName = v3Global.opt.mainTopName(); - if (!topName.empty()) { - if (topName == "-") topName = ""; - topArg = ", \"" + topName + "\""; - } + if (topName == "-") topName = ""; // Heavily commented output, as users are likely to look at or copy this code ofp()->putsHeader(); @@ -77,7 +74,7 @@ private: puts("// Construct the Verilated model, from Vtop.h generated from Verilating\n"); puts("const std::unique_ptr<" + topClassName() + "> topp{new " + topClassName() - + "{contextp.get()" + topArg + "}};\n"); + + "{contextp.get(), \"" + topName + "\"}};\n"); puts("\n"); puts("// Simulate until $finish\n"); diff --git a/test_regress/t/t_cover_main.out b/test_regress/t/t_cover_main.out index d762fd325..3dc822828 100644 --- a/test_regress/t/t_cover_main.out +++ b/test_regress/t/t_cover_main.out @@ -1,2 +1,2 @@ # SystemC::Coverage-3 -C 'ft/t_cover_main.vl9n4pagev_line/toblockS9-11hTOP.t' 1 +C 'ft/t_cover_main.vl9n4pagev_line/toblockS9-11h.t' 1 diff --git a/test_regress/t/t_timing_osc.out b/test_regress/t/t_timing_osc.out index b2c0182c3..afcbdeb10 100644 --- a/test_regress/t/t_timing_osc.out +++ b/test_regress/t/t_timing_osc.out @@ -1,27 +1,27 @@ $version Generated by VerilatedVcd $end $timescale 1fs $end - $scope module TOP $end - $scope module tb_osc $end - $var wire 1 # dco_out $end - $scope module dco $end - $var real 64 ' coarse_cw $end - $var real 64 ' medium_cw $end - $var real 64 ) fine_cw $end - $var wire 1 # rf_out $end - $var real 64 + coarse_ofst $end - $var real 64 - coarse_res $end - $var real 64 / medium_ofst $end - $var real 64 1 medium_res $end - $var real 64 3 fine_ofst $end - $var real 64 5 fine_res $end - $var real 64 7 coarse_delay $end - $var real 64 9 medium_delay $end - $var real 64 ; fine_delay $end - $var real 64 = jitter $end - $var wire 1 $ coarse_out $end - $var wire 1 % medium_out $end - $var wire 1 & fine_out $end - $upscope $end + $scope module $rootio $end + $upscope $end + $scope module tb_osc $end + $var wire 1 # dco_out $end + $scope module dco $end + $var real 64 ' coarse_cw $end + $var real 64 ' medium_cw $end + $var real 64 ) fine_cw $end + $var wire 1 # rf_out $end + $var real 64 + coarse_ofst $end + $var real 64 - coarse_res $end + $var real 64 / medium_ofst $end + $var real 64 1 medium_res $end + $var real 64 3 fine_ofst $end + $var real 64 5 fine_res $end + $var real 64 7 coarse_delay $end + $var real 64 9 medium_delay $end + $var real 64 ; fine_delay $end + $var real 64 = jitter $end + $var wire 1 $ coarse_out $end + $var wire 1 % medium_out $end + $var wire 1 & fine_out $end $upscope $end $upscope $end $enddefinitions $end diff --git a/test_regress/t/t_timing_timescale.out b/test_regress/t/t_timing_timescale.out index 041fa0bc7..e28ab2ef6 100644 --- a/test_regress/t/t_timing_timescale.out +++ b/test_regress/t/t_timing_timescale.out @@ -20,7 +20,7 @@ [9e-06] clkb is 1 [9.5e-06] clkb is 0 [1e-05] clkb is 1 -[1e-05] Finishing (TOP.t.bot) +[1e-05] Finishing (t.bot) *-* All Finished *-* -[10500] final (TOP.t) -[1.05e-05] final (TOP.t.bot) count was 21 +[10500] final (t) +[1.05e-05] final (t.bot) count was 21 diff --git a/test_regress/t/t_timing_trace.out b/test_regress/t/t_timing_trace.out index c5a28236b..f5a47ca02 100644 --- a/test_regress/t/t_timing_trace.out +++ b/test_regress/t/t_timing_trace.out @@ -1,17 +1,17 @@ $version Generated by VerilatedVcd $end $timescale 1ps $end - $scope module TOP $end - $scope module t $end - $var wire 32 * CLK_PERIOD [31:0] $end - $var wire 32 + CLK_HALF_PERIOD [31:0] $end - $var wire 1 # rst $end - $var wire 1 ( clk $end - $var wire 1 $ a $end - $var wire 1 ) b $end - $var wire 1 % c $end - $var wire 1 & d $end - $var event 1 ' ev $end - $upscope $end + $scope module $rootio $end + $upscope $end + $scope module t $end + $var wire 32 * CLK_PERIOD [31:0] $end + $var wire 32 + CLK_HALF_PERIOD [31:0] $end + $var wire 1 # rst $end + $var wire 1 ( clk $end + $var wire 1 $ a $end + $var wire 1 ) b $end + $var wire 1 % c $end + $var wire 1 & d $end + $var event 1 ' ev $end $upscope $end $enddefinitions $end diff --git a/test_regress/t/t_timing_trace_fst.out b/test_regress/t/t_timing_trace_fst.out index 0de0227ee..b95eb3cdb 100644 --- a/test_regress/t/t_timing_trace_fst.out +++ b/test_regress/t/t_timing_trace_fst.out @@ -1,5 +1,5 @@ $date - Sun Nov 5 12:08:16 2023 + Sun Sep 22 22:53:52 2024 $end $version @@ -8,7 +8,8 @@ $end $timescale 1ps $end -$scope module TOP $end +$scope module $rootio $end +$upscope $end $scope module t $end $var parameter 32 ! CLK_PERIOD [31:0] $end $var parameter 32 " CLK_HALF_PERIOD [31:0] $end @@ -20,7 +21,6 @@ $var logic 1 ' c $end $var logic 1 ( d $end $var event 1 ) ev $end $upscope $end -$upscope $end $enddefinitions $end #0 $dumpvars diff --git a/test_regress/t/t_trace_binary.out b/test_regress/t/t_trace_binary.out index 32d4f8ec5..6ba7d249c 100644 --- a/test_regress/t/t_trace_binary.out +++ b/test_regress/t/t_trace_binary.out @@ -1,11 +1,9 @@ $version Generated by VerilatedVcd $end -$date Sun Oct 9 14:08:37 2022 $end $timescale 1ps $end - - $scope module TOP $end - $scope module t $end - $var wire 32 # sig [31:0] $end - $upscope $end + $scope module $rootio $end + $upscope $end + $scope module t $end + $var wire 32 # sig [31:0] $end $upscope $end $enddefinitions $end diff --git a/test_regress/t/t_trace_class.out b/test_regress/t/t_trace_class.out index 41b74f075..caa31e989 100644 --- a/test_regress/t/t_trace_class.out +++ b/test_regress/t/t_trace_class.out @@ -1,9 +1,9 @@ $version Generated by VerilatedVcd $end $timescale 1ps $end - $scope module TOP $end - $scope module $unit::Cls__P0__Vclpkg $end - $var wire 32 # PARAM [31:0] $end - $upscope $end + $scope module $rootio $end + $upscope $end + $scope module $unit::Cls__P0__Vclpkg $end + $var wire 32 # PARAM [31:0] $end $upscope $end $enddefinitions $end diff --git a/test_regress/t/t_trace_event.out b/test_regress/t/t_trace_event.out index 5ed52d25b..33f528708 100644 --- a/test_regress/t/t_trace_event.out +++ b/test_regress/t/t_trace_event.out @@ -1,12 +1,12 @@ $version Generated by VerilatedVcd $end $timescale 1ps $end - $scope module TOP $end - $scope module t $end - $var event 1 # ev_test $end - $var wire 32 $ i [31:0] $end - $var wire 1 % toggle $end - $var wire 1 & clk $end - $upscope $end + $scope module $rootio $end + $upscope $end + $scope module t $end + $var event 1 # ev_test $end + $var wire 32 $ i [31:0] $end + $var wire 1 % toggle $end + $var wire 1 & clk $end $upscope $end $enddefinitions $end diff --git a/test_regress/t/t_trace_event_fst.out b/test_regress/t/t_trace_event_fst.out index 499b71791..bda112149 100644 --- a/test_regress/t/t_trace_event_fst.out +++ b/test_regress/t/t_trace_event_fst.out @@ -1,5 +1,5 @@ $date - Tue Sep 10 16:34:40 2024 + Sun Sep 22 22:54:12 2024 $end $version @@ -8,14 +8,14 @@ $end $timescale 1ps $end -$scope module TOP $end +$scope module $rootio $end +$upscope $end $scope module t $end $var event 1 ! ev_test $end $var int 32 " i [31:0] $end $var bit 1 # toggle $end $var bit 1 $ clk $end $upscope $end -$upscope $end $enddefinitions $end #0 $dumpvars diff --git a/test_regress/t/t_trace_param_override.out b/test_regress/t/t_trace_param_override.out index 2778ef8f4..c139f47f0 100644 --- a/test_regress/t/t_trace_param_override.out +++ b/test_regress/t/t_trace_param_override.out @@ -1,10 +1,10 @@ $version Generated by VerilatedVcd $end $timescale 1ps $end - $scope module TOP $end - $scope module t $end - $var wire 32 # POVERRODE [31:0] $end - $var wire 32 $ PORIG [31:0] $end - $upscope $end + $scope module $rootio $end + $upscope $end + $scope module t $end + $var wire 32 # POVERRODE [31:0] $end + $var wire 32 $ PORIG [31:0] $end $upscope $end $enddefinitions $end diff --git a/test_regress/t/t_trace_timing1.out b/test_regress/t/t_trace_timing1.out index 5d7ee2f0d..b829e1aca 100644 --- a/test_regress/t/t_trace_timing1.out +++ b/test_regress/t/t_trace_timing1.out @@ -1,12 +1,11 @@ $version Generated by VerilatedVcd $end $timescale 1ps $end - - $scope module TOP $end - $scope module t $end - $var wire 32 % CLOCK_CYCLE [31:0] $end - $var wire 1 # rst $end - $var wire 1 $ clk $end - $upscope $end + $scope module $rootio $end + $upscope $end + $scope module t $end + $var wire 32 % CLOCK_CYCLE [31:0] $end + $var wire 1 # rst $end + $var wire 1 $ clk $end $upscope $end $enddefinitions $end