From 056f72f27f1dd8ec006a04016f7ea2d82530f4bf Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Thu, 5 Jun 2008 20:49:52 +0000 Subject: [PATCH] Fix grammar error exposed with Verilog-Perl rev 55458 ++ -- fix git-svn-id: file://localhost/svn/verilator/trunk/verilator@1072 77ca24e4-aefa-0310-84f0-b9a241c72d87 --- src/verilog.y | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/verilog.y b/src/verilog.y index d120733af..32ae978c1 100644 --- a/src/verilog.y +++ b/src/verilog.y @@ -660,8 +660,8 @@ genItemList: genItem { $$ = $1; } genItem: modOrGenItem { $$ = $1; } | yCASE '(' expr ')' genCaseListE yENDCASE { $$ = new AstGenCase($1,$3,$5); } - | yIF expr genItemBlock %prec prLOWER_THAN_ELSE { $$ = new AstGenIf($1,$2,$3,NULL); } - | yIF expr genItemBlock yELSE genItemBlock { $$ = new AstGenIf($1,$2,$3,$5); } + | yIF '(' expr ')' genItemBlock %prec prLOWER_THAN_ELSE { $$ = new AstGenIf($1,$3,$5,NULL); } + | yIF '(' expr ')' genItemBlock yELSE genItemBlock { $$ = new AstGenIf($1,$3,$5,$7); } | yFOR '(' varRefBase '=' expr ';' expr ';' varRefBase '=' expr ')' genItemBlock { $$ = new AstGenFor($1, new AstAssign($4,$3,$5) ,$7, new AstAssign($10,$9,$11) @@ -931,8 +931,8 @@ stmt: ';' { $$ = NULL; } // Case/If stateCaseForIf: caseStmt caseAttrE caseListE yENDCASE { $$ = $1; if ($3) $1->addItemsp($3); } - | yIF expr stmtBlock %prec prLOWER_THAN_ELSE { $$ = new AstIf($1,$2,$3,NULL); } - | yIF expr stmtBlock yELSE stmtBlock { $$ = new AstIf($1,$2,$3,$5); } + | yIF '(' expr ')' stmtBlock %prec prLOWER_THAN_ELSE { $$ = new AstIf($1,$3,$5,NULL); } + | yIF '(' expr ')' stmtBlock yELSE stmtBlock { $$ = new AstIf($1,$3,$5,$7); } | yFOR '(' varRefBase '=' expr ';' expr ';' varRefBase '=' expr ')' stmtBlock { $$ = new AstFor($1, new AstAssign($4,$3,$5) ,$7, new AstAssign($10,$9,$11)