2008-04-24 15:14:40 +00:00
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// $Id$
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2006-08-26 11:35:28 +00:00
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2003 by Wilson Snyder.
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module t (/*AUTOARG*/);
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reg [3:0] a;
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reg [99:0] x;
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initial begin
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a = 4'b010x;
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if (a[3:2] !== 2'b01) $stop;
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if (|a !== 1'b1) $stop;
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if (&a !== 1'b0) $stop;
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x = 100'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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