2024-09-08 17:00:03 +00:00
|
|
|
#!/usr/bin/env python3
|
2024-05-17 14:38:34 +00:00
|
|
|
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
|
|
|
|
#
|
|
|
|
# Copyright 2024 by Wilson Snyder. This program is free software; you
|
|
|
|
# can redistribute it and/or modify it under the terms of either the GNU
|
|
|
|
# Lesser General Public License Version 3 or the Perl Artistic License
|
|
|
|
# Version 2.0.
|
|
|
|
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
|
|
|
|
|
2024-09-08 17:00:03 +00:00
|
|
|
import vltest_bootstrap
|
2024-05-17 14:38:34 +00:00
|
|
|
|
2024-09-08 17:00:03 +00:00
|
|
|
test.scenarios('simulator')
|
2024-09-21 14:04:58 +00:00
|
|
|
test.top_filename = "t/t_opt_const.v"
|
2024-05-17 14:38:34 +00:00
|
|
|
|
2024-09-21 14:04:58 +00:00
|
|
|
test.compile(verilator_flags2=["-Wno-UNOPTTHREADS", "--stats", test.t_dir + "/t_opt_const.cpp"])
|
2024-05-17 14:38:34 +00:00
|
|
|
|
2024-09-08 17:00:03 +00:00
|
|
|
test.execute()
|
2024-05-17 14:38:34 +00:00
|
|
|
|
2024-09-08 17:00:03 +00:00
|
|
|
if test.vlt:
|
2024-11-10 17:23:11 +00:00
|
|
|
test.file_grep(test.stats, r'Optimizations, Const bit op reduction\s+(\d+)', 40)
|
2024-05-17 14:38:34 +00:00
|
|
|
|
2024-09-08 17:00:03 +00:00
|
|
|
test.passes()
|