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24 lines
506 B
Systemverilog
24 lines
506 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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module t();
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initial begin
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int queue[$];
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queue.insert(0, 0);
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if (queue.size() != 1) $stop;
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queue.insert(1, 1);
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if (queue.size() != 2) $stop;
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if (queue[0] != 0) $stop;
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if (queue[1] != 1) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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