verilator/test_regress/t/t_assert_synth_full.out

[0] -Info: t_assert_synth.v:115: top.t.test_info: Start of $info test
[0] -Info: t_assert_synth.v:116: top.t.test_info: Middle of $info test
[0] -Info: t_assert_synth.v:117: top.t.test_info: End of $info test
[40] %Error: t_assert_synth.v:31: Assertion failed in top.t: synthesis full_case, but non-match found
%Error: t/t_assert_synth.v:31: Verilog $stop
Aborting...
Fix info message prints under --assert (#4036) (#4053) 2023-03-24 23:22:48 +00:00			`[0] -Info: t_assert_synth.v:115: top.t.test_info: Start of $info test`
			`[0] -Info: t_assert_synth.v:116: top.t.test_info: Middle of $info test`
			`[0] -Info: t_assert_synth.v:117: top.t.test_info: End of $info test`
Add SPDX license identifiers. No functional change. 2020-03-21 15:24:24 +00:00			`[40] %Error: t_assert_synth.v:31: Assertion failed in top.t: synthesis full_case, but non-match found`
			`%Error: t/t_assert_synth.v:31: Verilog $stop`
Tests: Favor use of expect_filename. No functional change. 2020-03-14 21:42:15 +00:00			`Aborting...`