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Tests: Favor use of expect_filename. No functional change.

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This commit is contained in:
Wilson Snyder 2020-03-14 17:42:15 -04:00
parent e6c91f59ab
commit 0a755e6ecf
26 changed files with 50 additions and 35 deletions
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3
test_regress/t/t_assert_synth_full.out Normal file
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@ -0,0 +1,3 @@
[40] %Error: t_assert_synth.v:30: Assertion failed in top.t: synthesis full_case, but non-match found
%Error: t/t_assert_synth.v:30: Verilog $stop
Aborting...

3
test_regress/t/t_assert_synth_full.pl
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@ -20,8 +20,7 @@ compile(
execute(
check_finished => 0,
fails => $Self->{vlt_all},
expect =>
'%Error: t_assert_synth.v:30: Assertion failed in top.t: synthesis full_case'
expect_filename => $Self->{golden_filename},
);
ok(1);

3
test_regress/t/t_assert_synth_parallel.out Normal file
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@ -0,0 +1,3 @@
[40] %Error: t_assert_synth.v:49: Assertion failed in top.t: synthesis parallel_case, but multiple matches found
%Error: t/t_assert_synth.v:49: Verilog $stop
Aborting...

3
test_regress/t/t_assert_synth_parallel.pl
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@ -20,8 +20,7 @@ compile(
execute(
check_finished => 0,
fails => $Self->{vlt_all},
expect =>
'%Error: t_assert_synth.v:\d+: Assertion failed in top.t: synthesis parallel_case'
expect_filename => $Self->{golden_filename},
);
ok(1);

3
test_regress/t/t_assert_synth_parallel_vlt.out Normal file
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@ -0,0 +1,3 @@
[40] %Error: t_assert_synth.v:54: Assertion failed in top.t: synthesis parallel_case, but multiple matches found
%Error: t/t_assert_synth.v:54: Verilog $stop
Aborting...

3
test_regress/t/t_assert_synth_parallel_vlt.pl
View File

@ -20,8 +20,7 @@ compile(
execute(
check_finished => 0,
fails => $Self->{vlt_all},
expect =>
'%Error: t_assert_synth.v:\d+: Assertion failed in top.t: synthesis parallel_case'
expect_filename => $Self->{golden_filename},
);
ok(1);

5
test_regress/t/t_preproc_inc_bad.out Normal file
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@ -0,0 +1,5 @@
%Error: t/t_preproc_inc_inc_bad.vh:10: syntax error, unexpected endmodule, expecting IDENTIFIER
endmodule
^~~~~~~~~
t/t_preproc_inc_bad.v:9: ... note: In file included from t_preproc_inc_bad.v
%Error: Exiting due to

3
test_regress/t/t_preproc_inc_bad.pl
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@ -12,8 +12,7 @@ scenarios(vlt => 1);
lint(
fails => 1,
# The .vh file has the error, not the .v file
expect =>
'%Error: t/t_preproc_inc_inc_bad.vh:10: syntax error, unexpected endmodule, expecting IDENTIFIER'
expect_filename => $Self->{golden_filename},
);
ok(1);

2
test_regress/t/t_sys_readmem_bad_addr.out Normal file
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@ -0,0 +1,2 @@
%Error: t/t_sys_readmem_bad_addr.mem:8: $readmem file address beyond bounds of array
Aborting...

3
test_regress/t/t_sys_readmem_bad_addr.pl
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@ -14,8 +14,7 @@ compile(
execute(
fails => $Self->{vlt_all},
expect =>
'%Error: t/t_sys_readmem_bad_addr.mem:\d+: \$readmem file address beyond bounds of array',
expect_filename => $Self->{golden_filename},
);
ok(1);

2
test_regress/t/t_sys_readmem_bad_digit.out Normal file
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@ -0,0 +1,2 @@
%Error: t/t_sys_readmem_bad_digit.mem:7: $readmemb (binary) file contains hex characters
Aborting...

3
test_regress/t/t_sys_readmem_bad_digit.pl
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@ -14,8 +14,7 @@ compile(
execute(
fails => $Self->{vlt_all},
expect =>
'%Error: t/t_sys_readmem_bad_digit.mem:\d+: \$readmemb \(binary\) file contains hex characters',
expect_filename => $Self->{golden_filename},
);
ok(1);

2
test_regress/t/t_sys_readmem_bad_end.out Normal file
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@ -0,0 +1,2 @@
%Error: t/t_sys_readmem_bad_end.mem:11: $readmem file ended before specified final address (IEEE 2017 21.4)
Aborting...

3
test_regress/t/t_sys_readmem_bad_end.pl
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@ -14,8 +14,7 @@ compile(
execute(
fails => $Self->{vlt_all},
expect =>
'%Error: t/t_sys_readmem_bad_end.mem:\d+: \$readmem file ended before specified final address',
expect_filename => $Self->{golden_filename},
);
ok(1);

2
test_regress/t/t_sys_readmem_bad_notfound.out Normal file
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@ -0,0 +1,2 @@
%Error: t/t_sys_readmem_bad_NOTFOUND.mem:0: $readmem file not found
Aborting...

3
test_regress/t/t_sys_readmem_bad_notfound.pl
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@ -14,8 +14,7 @@ compile(
execute(
fails => $Self->{vlt_all},
expect =>
'%Error: t/t_sys_readmem_bad_NOTFOUND.mem:\d+: \$readmem file not found',
expect_filename => $Self->{golden_filename},
);
ok(1);

4
test_regress/t/t_uniqueif_fail1.out Normal file
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@ -0,0 +1,4 @@
testing fail 1: 1
[10] %Error: t_uniqueif.v:73: Assertion failed in top.t: 'unique if' statement violated
%Error: t/t_uniqueif.v:73: Verilog $stop
Aborting...

5
test_regress/t/t_uniqueif_fail1.pl
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@ -20,10 +20,7 @@ compile(
execute(
fails => $Self->{vlt_all},
expect =>
'.*%Error: t_uniqueif.v:\d+: Assertion failed in top.t: \'unique if\' statement violated
%Error: t/t_uniqueif.v:\d+: Verilog \$stop
.*',
expect_filename => $Self->{golden_filename},
);
ok(1);

3
test_regress/t/t_uniqueif_fail2.out Normal file
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@ -0,0 +1,3 @@
[10] %Error: t_uniqueif.v:81: Assertion failed in top.t: 'unique if' statement violated
%Error: t/t_uniqueif.v:81: Verilog $stop
Aborting...

5
test_regress/t/t_uniqueif_fail2.pl
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@ -20,10 +20,7 @@ compile(
execute(
fails => $Self->{vlt_all},
expect =>
'.*%Error: t_uniqueif.v:\d+: Assertion failed in top.t: \'unique if\' statement violated
%Error: t/t_uniqueif.v:\d+: Verilog \$stop
.*',
expect_filename => $Self->{golden_filename},
);
ok(1);

3
test_regress/t/t_uniqueif_fail3.out Normal file
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@ -0,0 +1,3 @@
[10] %Error: t_uniqueif.v:89: Assertion failed in top.t: 'unique if' statement violated
%Error: t/t_uniqueif.v:89: Verilog $stop
Aborting...

5
test_regress/t/t_uniqueif_fail3.pl
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@ -20,10 +20,7 @@ compile(
execute(
fails => $Self->{vlt_all},
expect =>
'.*%Error: t_uniqueif.v:\d+: Assertion failed in top.t: \'unique if\' statement violated
%Error: t/t_uniqueif.v:\d+: Verilog \$stop
.*',
expect_filename => $Self->{golden_filename},
);
ok(1);

3
test_regress/t/t_uniqueif_fail4.out Normal file
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@ -0,0 +1,3 @@
[10] %Error: t_uniqueif.v:101: Assertion failed in top.t: 'unique if' statement violated
%Error: t/t_uniqueif.v:101: Verilog $stop
Aborting...

5
test_regress/t/t_uniqueif_fail4.pl
View File

@ -20,10 +20,7 @@ compile(
execute(
fails => $Self->{vlt_all},
expect =>
'.*%Error: t_uniqueif.v:\d+: Assertion failed in top.t: \'unique if\' statement violated
%Error: t/t_uniqueif.v:\d+: Verilog \$stop
.*',
expect_filename => $Self->{golden_filename},
);
ok(1);

2
test_regress/t/t_var_overwidth_bad.out Normal file
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@ -0,0 +1,2 @@
%Error: unknown:0: Testbench C set input 'clk' to value that overflows what the signal's width can fit
Aborting...

4
test_regress/t/t_var_overwidth_bad.pl
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@ -16,9 +16,7 @@ compile(
execute(
fails => 1,
expect =>
qr{%Error: unknown:0: Testbench C set input 'clk' to value that overflows what the signal's width can fit
Aborting....*}
expect_filename => $Self->{golden_filename},
);
ok(1);