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13 lines
327 B
Systemverilog
13 lines
327 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2009 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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primitive udp_x (a_bad, b, c_bad);
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tri a_bad;
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output b;
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output c_bad;
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endtable // BAD
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endprimitive
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