2006-12-18 19:49:36 +00:00
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// $Id$
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2006-08-26 11:35:28 +00:00
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2003 by Wilson Snyder.
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`include "verilated.v"
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module t_clk_flop (/*AUTOARG*/
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// Outputs
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q, q2,
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// Inputs
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clk, clk2, a
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);
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parameter WIDTH=8;
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input clk;
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input clk2;
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input [(WIDTH-1):0] a;
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output [(WIDTH-1):0] q;
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output [(WIDTH-1):0] q2;
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reg [(WIDTH-1):0] q;
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reg [(WIDTH-1):0] q2;
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always @ (posedge clk) q<=a;
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always @ (posedge clk2) q2<=a;
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endmodule
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