verilator/test_regress/t/t_savable_coverage_bad.v

9 lines
248 B
Systemverilog
Raw Normal View History

2022-11-05 15:40:34 +00:00
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2020 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/);
endmodule