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30 lines
705 B
Systemverilog
30 lines
705 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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// Note $sformatf already tested elsewhere
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reg [3:0] n;
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reg [63:0] q;
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reg [16*8:1] wide;
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string str;
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initial begin
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n = 4'b1100;
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q = 64'h1234_5678_abcd_0123;
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wide = "hello-there12345";
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str = $psprintf("n=%b q=%d w=%s", n, q, wide);
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`ifdef TEST_VERBOSE $display("str=%0s",str); `endif
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if (str !== "n=1100 q= 1311768467750060323 w=hello-there12345") $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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