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32 lines
627 B
Systemverilog
32 lines
627 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Tudor Timi.
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// SPDX-License-Identifier: CC0-1.0
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class svunit_base;
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function new(string name);
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endfunction
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endclass
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class svunit_testcase extends svunit_base;
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function new(string name);
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super.new(name);
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endfunction
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endclass
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module dut_unit_test;
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svunit_testcase svunit_ut = new("dut_ut");
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endmodule
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module t(/*AUTOARG*/);
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dut_unit_test dut_ut();
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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