Fix super.new missing data type (#4147).

Changes

@@ -29,6 +29,7 @@ Verilator 5.011 devel
 * Fix crash caused by $display() optimization (#4165) (#4166). [Tudor Timi]
 * Fix arrays of unpacked structs (#4173). [Risto Pejašinović]
 * Fix $fscanf of decimals overflowing variables (#4174). [Ahmed El-Mahmoudy]
+* Fix super.new missing data type (#4147). [Tudor Timi]
 * Fix detection of wire/reg duplicates.
 * Fix false IMPLICITSTATIC on package functions.
 

src/V3Width.cpp

@@ -3755,7 +3755,9 @@ private:
     void visit(AstNew* nodep) override {
         if (nodep->didWidth()) return;
         AstClass* classp = nullptr;
+        bool assign = false;
         if (VN_IS(nodep->backp(), Assign)) {  // assignment case
+            assign = true;
             AstClassRefDType* const refp
                 = m_vup ? VN_CAST(m_vup->dtypeNullSkipRefp(), ClassRefDType) : nullptr;
             if (!refp) {  // e.g. int a = new;
@@ -3783,9 +3785,9 @@ private:
             classp = VN_CAST(nodep->classOrPackagep(), Class);
             UASSERT_OBJ(classp, nodep, "Unlinked classOrPackagep()");
             UASSERT_OBJ(nodep->taskp(), nodep, "Unlinked taskp()");
-            nodep->dtypeFrom(nodep->taskp());
         }
         userIterate(nodep->taskp(), nullptr);
+        if (!assign) nodep->dtypeFrom(nodep->taskp());
         processFTaskRefArgs(nodep);
     }
     void visit(AstNewCopy* nodep) override {

test_regress/t/t_class_super_new2.pl

@@ -0,0 +1,21 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2023 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;

test_regress/t/t_class_super_new2.v

@@ -0,0 +1,31 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2023 by Tudor Timi.
+// SPDX-License-Identifier: CC0-1.0
+
+class svunit_base;
+   function new(string name);
+   endfunction
+endclass
+
+class svunit_testcase extends svunit_base;
+   function new(string name);
+      super.new(name);
+   endfunction
+endclass
+
+module dut_unit_test;
+   svunit_testcase svunit_ut = new("dut_ut");
+endmodule
+
+module t(/*AUTOARG*/);
+
+   dut_unit_test dut_ut();
+
+   initial begin
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+endmodule