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30 lines
671 B
Systemverilog
30 lines
671 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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package uvm_pkg;
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class uvm_reg_field; // extends uvm_object;
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function void configure(bit overde, bit is_rand);
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if (overde) is_rand = 0;
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if (!is_rand) ; // value.rand_mode(0);
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// See issue #4567
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endfunction
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endclass
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endpackage
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module t(/*AUTOARG*/);
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initial begin
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uvm_pkg::uvm_reg_field c = new;
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c.configure(1, 0);
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c.configure(0, 0);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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