Fix compile warning on unused member function variable (#4567).

This commit is contained in:
Wilson Snyder 2023-10-18 08:09:42 -04:00
parent 8b44a54bb2
commit 493f1da266
4 changed files with 55 additions and 3 deletions

View File

@ -41,6 +41,7 @@ Verilator 5.017 devel
* Fix broken link error for enum references (#4551). [Anthony Donlon]
* Fix instance arrays connecting to array of structs (#4557). [raphmaster]
* Fix shift to remove operation side effects (#4563).
* Fix compile warning on unused member function variable (#4567).
* Fix preprocessor to show `line 2 on resumed file.

View File

@ -443,14 +443,15 @@ m4_foreach([cflag],[
[-Qunused-arguments],
[-Wno-bool-operation],
[-Wno-constant-logical-operand],
[-Wno-tautological-bitwise-compare],
[-Wno-parentheses-equality],
[-Wno-shadow],
[-Wno-sign-compare],
[-Wno-tautological-bitwise-compare],
[-Wno-uninitialized],
[-Wno-unused-but-set-parameter],
[-Wno-unused-but-set-variable],
[-Wno-unused-parameter],
[-Wno-unused-variable],
[-Wno-shadow]],[
[-Wno-unused-variable]],[
_MY_CXX_CHECK_OPT(CFG_CXXFLAGS_NO_UNUSED,cflag)
# CMake will test what flags work itself, so pass all flags through to it
CFG_CXX_FLAGS_CMAKE="$CFG_CXX_FLAGS_CMAKE cflag"

View File

@ -0,0 +1,21 @@
#!/usr/bin/env perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2023 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(simulator => 1);
compile(
);
execute(
check_finished => 1,
);
ok(1);
1;

View File

@ -0,0 +1,29 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2023 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
package uvm_pkg;
class uvm_reg_field; // extends uvm_object;
function void configure(bit overde, bit is_rand);
if (overde) is_rand = 0;
if (!is_rand) ; // value.rand_mode(0);
// See issue #4567
endfunction
endclass
endpackage
module t(/*AUTOARG*/);
initial begin
uvm_pkg::uvm_reg_field c = new;
c.configure(1, 0);
c.configure(0, 0);
$write("*-* All Finished *-*\n");
$finish;
end
endmodule