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16 lines
406 B
Systemverilog
16 lines
406 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2012 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/);
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if ($test$plusargs("BAD-non-constant")) begin
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initial $stop;
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end
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case (1)
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$test$plusargs("BAD-non-constant"): initial $stop;
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endcase
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endmodule
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