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20 lines
437 B
Systemverilog
20 lines
437 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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int valuea;
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int valueb;
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initial begin
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valuea = $random(10);
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valueb = $random(10);
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if (valuea !== valueb) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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