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Fix message for seeded random.

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This commit is contained in:
Wilson Snyder 2020-05-10 21:15:48 -04:00
parent ba7b3fd60f
commit 15f63d12d5
4 changed files with 50 additions and 1 deletions
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3
src/verilog.y
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@ -3433,7 +3433,8 @@ system_f_call_or_t<nodep>: // IEEE: part of system_tf_call (can be task or func)
| yD_PAST '(' expr ',' expr ',' expr ')' { $1->v3error("Unsupported: $past expr2 and clock arguments"); $$ = $3; }
| yD_PAST '(' expr ',' expr ',' expr ',' expr')' { $1->v3error("Unsupported: $past expr2 and clock arguments"); $$ = $3; }
| yD_POW '(' expr ',' expr ')' { $$ = new AstPowD($1,$3,$5); }
| yD_RANDOM '(' expr ')' { $$ = NULL; $1->v3error("Unsupported: Seeding $random doesn't map to C++, use $c(\"srand\")"); }
// // Seeding is unsupported as would be slow to invalidate all per-thread RNGs
| yD_RANDOM '(' expr ')' { $$ = new AstRand($1); $1->v3error("Unsupported: Seed on $random. Suggest use +verilator+seed+ runtime flag"); }
| yD_RANDOM parenE { $$ = new AstRand($1); }
| yD_REALTIME parenE { $$ = new AstTimeD($1, VTimescale(VTimescale::NONE)); }
| yD_REALTOBITS '(' expr ')' { $$ = new AstRealToBits($1,$3); }

7
test_regress/t/t_sys_rand_seed.out Normal file
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@ -0,0 +1,7 @@
%Error: t/t_sys_rand_seed.v:13:16: Unsupported: Seed on $random. Suggest use +verilator+seed+ runtime flag
13 | valuea = $random(10);
| ^~~~~~~
%Error: t/t_sys_rand_seed.v:14:16: Unsupported: Seed on $random. Suggest use +verilator+seed+ runtime flag
14 | valueb = $random(10);
| ^~~~~~~
%Error: Exiting due to

22
test_regress/t/t_sys_rand_seed.pl Executable file
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@ -0,0 +1,22 @@
#!/usr/bin/env perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(simulator => 1);
compile(
fails => $Self->{vlt_all},
expect_filename => $Self->{golden_filename},
);
execute(
) if !$Self->{vlt_all};
ok(1);
1;

19
test_regress/t/t_sys_rand_seed.v Normal file
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@ -0,0 +1,19 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2020 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t;
int valuea;
int valueb;
initial begin
valuea = $random(10);
valueb = $random(10);
if (valuea !== valueb) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule