verilator/test_regress/t/t_flag_wpedantic_bad.v

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2019-11-16 16:59:21 +00:00
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2019 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
2019-11-16 16:59:21 +00:00
module t (/*AUTOARG*/);
reg global;
endmodule