2019-07-12 02:09:30 +00:00
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%Warning-CDCRSTLOGIC: t/t_cdc_async_bad.v:27: Logic in path that feeds async reset, via signal: 't.rst2_bad_n'
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2019-07-15 01:42:03 +00:00
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wire rst2_bad_n = rst0_n | rst1_n;
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^
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2019-05-31 00:30:59 +00:00
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... Use "/* verilator lint_off CDCRSTLOGIC */" and lint_on around source to disable this message.
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2018-11-03 18:59:04 +00:00
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%Warning-CDCRSTLOGIC: See details in obj_vlt/t_cdc_async_bad/Vt_cdc_async_bad__cdc.txt
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2019-07-12 02:09:30 +00:00
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%Warning-CDCRSTLOGIC: t/t_cdc_async_bad.v:52: Logic in path that feeds async reset, via signal: 't.rst6a_bad_n'
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2019-07-15 01:42:03 +00:00
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wire rst6a_bad_n = rst6_bad_n ^ $c1("0");
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^
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2019-07-12 02:09:30 +00:00
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%Warning-CDCRSTLOGIC: t/t_cdc_async_bad.v:53: Logic in path that feeds async reset, via signal: 't.rst6b_bad_n'
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2019-07-15 01:42:03 +00:00
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wire rst6b_bad_n = rst6_bad_n ^ $c1("1");
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^
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2018-11-03 18:59:04 +00:00
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%Error: Exiting due to
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