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Error continuation lines no longer have %Error prefix.

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This commit is contained in:
Wilson Snyder 2019-05-30 20:30:59 -04:00
parent c0be8bcefb
commit a58e7d94ec
103 changed files with 275 additions and 261 deletions
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2
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@ -6,6 +6,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
*** Add --quiet-exit, bug1436. [Todd Strader]
**** Error continuation lines no longer have %Error prefix.
**** Support VerilatedFstC set_time_unit, bug1433. [Pieter Kapsenberg]
**** Mark infrequently called functions with GCC cold attribute.

10
src/V3Error.cpp
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@ -158,7 +158,7 @@ void V3Error::suppressThisWarning() {
}
string V3Error::warnMore() {
return msgPrefix();
return string(msgPrefix().size(), ' ');
}
void V3Error::v3errorEnd(std::ostringstream& sstr) {
@ -182,13 +182,13 @@ void V3Error::v3errorEnd(std::ostringstream& sstr) {
&& !s_pretendError[s_errorCode]) {
s_describedEachWarn[s_errorCode] = true;
if (s_errorCode>=V3ErrorCode::EC_FIRST_WARN && !s_describedWarnings) {
std::cerr<<msgPrefix()<<"Use \"/* verilator lint_off "<<s_errorCode.ascii()
std::cerr<<warnMore()<<"... Use \"/* verilator lint_off "<<s_errorCode.ascii()
<<" */\" and lint_on around source to disable this message."<<endl;
s_describedWarnings = true;
}
if (s_errorCode.dangerous()) {
std::cerr<<msgPrefix()<<"*** See the manual before disabling this,"<<endl;
std::cerr<<msgPrefix()<<"else you may end up with different sim results."<<endl;
std::cerr<<warnMore()<<"*** See the manual before disabling this,"<<endl;
std::cerr<<warnMore()<<"else you may end up with different sim results."<<endl;
}
}
// If first warning is not the user's fault (internal/unsupported) then give the website
@ -209,7 +209,7 @@ void V3Error::v3errorEnd(std::ostringstream& sstr) {
if (!inFatal) {
inFatal = true;
if (s_tellManual==1) {
std::cerr<<msgPrefix()<<"See the manual and http://www.veripool.org/verilator for more assistance."<<endl;
std::cerr<<warnMore()<<"... See the manual and http://www.veripool.org/verilator for more assistance."<<endl;
s_tellManual = 2;
}
#ifndef _V3ERROR_NO_GLOBAL_

2
src/V3Graph.cpp
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@ -277,7 +277,7 @@ void V3Graph::loopsMessageCb(V3GraphVertex* vertexp) {
void V3Graph::loopsVertexCb(V3GraphVertex* vertexp) {
// Needed here as V3GraphVertex<< isn't defined until later in header
std::cerr<<"-Info-Loop: "<<cvtToHex(vertexp)<<" "<<vertexp<<endl;
if (debug()) std::cerr<<"-Info-Loop: "<<cvtToHex(vertexp)<<" "<<vertexp<<endl;
}
void V3Graph::dump(std::ostream& os) {

5
src/V3LinkCells.cpp
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@ -79,8 +79,9 @@ public:
void LinkCellsGraph::loopsMessageCb(V3GraphVertex* vertexp) {
if (LinkCellsVertex* vvertexp = dynamic_cast<LinkCellsVertex*>(vertexp)) {
vvertexp->modp()->v3error("Unsupported: Recursive multiple modules (module instantiates something leading back to itself): "
<<vvertexp->modp()->prettyName());
vvertexp->modp()->v3error("Note self-recursion (module instantiating itself directly) is supported.");
<<vvertexp->modp()->prettyName()<<endl
<<V3Error::warnMore()
<<"... Note self-recursion (module instantiating itself directly) is supported.");
V3Error::abortIfErrors();
} else { // Everything should match above, but...
v3fatalSrc("Recursive instantiations");

8
src/V3LinkLevel.cpp
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@ -59,9 +59,13 @@ void V3LinkLevel::modSortByLevel() {
nodep; nodep=VN_CAST(nodep->nextp(), NodeModule)) {
if (nodep->level()<=2) {
if (topp) {
static int warnedOnce = 0;
nodep->v3warn(E_MULTITOP, "Unsupported: Multiple top level modules: "
<<nodep->prettyName()<<" and "<<topp->prettyName());
nodep->v3warn(E_MULTITOP, "Fix, or use --top-module option to select which you want.");
<<nodep->prettyName()<<" and "<<topp->prettyName()<<endl
<<(!warnedOnce++
? (nodep->warnMore()
+"... Fix, or use --top-module option to select which you want.")
: ""));
}
topp = nodep;
}

16
src/V3Number.cpp
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@ -150,14 +150,14 @@ void V3Number::V3NumberCreate(AstNode* nodep, const char* sourcep, FileLine* fl)
product.opMul(*this, ten);
this->opAdd(product, addend);
if (product.bitsValue(width(), 4)) { // Overflowed
v3error("Too many digits for "<<width()<<" bit number: "<<sourcep);
if (!m_sized) {
static int warned = false;
if (!warned++) {
v3error("As that number was unsized ('d...)"
" it is limited to 32 bits (IEEE 2017 5.7.1)");
}
}
static int warned = 0;
v3error("Too many digits for "<<width()<<" bit number: "<<sourcep
<<std::endl
<<((!m_sized && !warned++)
? (V3Error::warnMore()+"... As that number was unsized"
+" ('d...) it is limited to 32 bits (IEEE 2017 5.7.1)\n"
+ V3Error::warnMore()+"... Suggest adding a size to it.")
: ""));
while (*(cp+1)) cp++; // Skip ahead so don't get multiple warnings
}
}

6
src/V3Options.cpp
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@ -375,13 +375,13 @@ void V3Options::filePathLookedMsg(FileLine* fl, const string& modname) {
if (m_impp->m_incDirUsers.empty()) {
fl->v3error("This may be because there's no search path specified with -I<dir>."<<endl);
}
fl->v3error("Looked in:"<<endl);
std::cerr<<V3Error::warnMore()<<"... Looked in:"<<endl;
for (std::list<string>::iterator dirIter=m_impp->m_incDirUsers.begin();
dirIter!=m_impp->m_incDirUsers.end(); ++dirIter) {
for (std::list<string>::iterator extIter=m_impp->m_libExtVs.begin();
extIter != m_impp->m_libExtVs.end(); ++extIter) {
string fn = V3Os::filenameFromDirBase(*dirIter, modname+*extIter);
fl->v3error(" "<<fn<<endl);
std::cerr<<V3Error::warnMore()<<" "<<fn<<endl;
}
}
for (std::list<string>::iterator dirIter=m_impp->m_incDirFallbacks.begin();
@ -389,7 +389,7 @@ void V3Options::filePathLookedMsg(FileLine* fl, const string& modname) {
for (std::list<string>::iterator extIter=m_impp->m_libExtVs.begin();
extIter != m_impp->m_libExtVs.end(); ++extIter) {
string fn = V3Os::filenameFromDirBase(*dirIter, modname+*extIter);
fl->v3error(" "<<fn<<endl);
std::cerr<<V3Error::warnMore()<<" "<<fn<<endl;
}
}
}

10
src/V3Order.cpp
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@ -117,12 +117,14 @@ static bool domainsExclusive(const AstSenTree* fromp, const AstSenTree* top);
void OrderGraph::loopsVertexCb(V3GraphVertex* vertexp) {
if (debug()) cout<<"-Info-Loop: "<<vertexp<<" "<<endl;
if (OrderLogicVertex* vvertexp = dynamic_cast<OrderLogicVertex*>(vertexp)) {
std::cerr<<V3Error::msgPrefix()<<" Example path: "
<<vvertexp->nodep()->fileline()<<" "<<vvertexp->nodep()->typeName()<<endl;
std::cerr<<vvertexp->nodep()->fileline()->warnMore()
<<" Example path: "
<<vvertexp->nodep()->typeName()<<endl;
}
if (OrderVarVertex* vvertexp = dynamic_cast<OrderVarVertex*>(vertexp)) {
std::cerr<<V3Error::msgPrefix()<<" Example path: "
<<vvertexp->varScp()->fileline()<<" "<<vvertexp->varScp()->prettyName()<<endl;
std::cerr<<vvertexp->varScp()->fileline()->warnMore()
<<" Example path: "
<<vvertexp->varScp()->prettyName()<<endl;
}
};

5
src/V3Simulate.h
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@ -186,7 +186,8 @@ public:
for (std::deque<SimStackNode*>::iterator it=m_callStack.begin();
it != m_callStack.end(); ++it) {
AstFuncRef* funcp = (*it)->m_funcp;
stack<<"\nCalled from:\n"<<funcp->fileline()<<" "
stack<<"\n "<<funcp->fileline()
<<"... Called from "
<<funcp->prettyName()<<"() with parameters:";
V3TaskConnects* tconnects = (*it)->m_tconnects;
for (V3TaskConnects::iterator conIt = tconnects->begin();
@ -194,7 +195,7 @@ public:
AstVar* portp = conIt->first;
AstNode* pinp = conIt->second->exprp();
AstNodeDType* dtypep = pinp->dtypep();
stack<<"\n "<<portp->prettyName(
stack<<"\n "<<portp->prettyName(
)<<" = "<<prettyNumber(fetchNumber(pinp), dtypep);
}
}

2
src/V3SymTable.h
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@ -239,7 +239,7 @@ public:
}
}
if (scopes=="") scopes="<no cells found>";
std::cerr<<V3Error::msgPrefix()<<" Known scopes under '"<<prettyName<<"': "
std::cerr<<V3Error::warnMore()<<"... Known scopes under '"<<prettyName<<"': "
<<scopes<<endl;
if (debug()) dump(std::cerr,"\t\t KnownScope: ", 1);
}

4
src/V3Tristate.cpp
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@ -455,8 +455,8 @@ class TristateVisitor : public TristateBaseVisitor {
varp->user3p(pullp); // save off to indicate the pull direction
} else {
if (oldpullp->direction() != pullp->direction()) {
pullp->v3error("Unsupported: Conflicting pull directions.");
oldpullp->v3error("... Location of conflicting pull.");
pullp->v3error("Unsupported: Conflicting pull directions.\n"
<<oldpullp->warnMore()<<"... Location of conflicting pull.");
}
}
}

6
src/verilog.l
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@ -124,8 +124,10 @@ void yyerror(const char* errmsg) {
&& PARSEP->curBisonVal().token == yP_COLONCOLON) {
static int warned = false;
if (!warned++) {
PARSEP->fileline()->v3error("Perhaps '"+*PARSEP->prevBisonVal().strp
+"' is a package which needs to be predeclared? (IEEE 2017 26.3)");
std::cerr<<PARSEP->fileline()->warnMore()
<<("... Perhaps '"+*PARSEP->prevBisonVal().strp
+"' is a package which needs to be predeclared? (IEEE 2017 26.3)")
<<std::endl;
}
}
}

9
src/verilog.y
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@ -199,8 +199,13 @@ int V3ParseGrammar::s_modTypeImpNum = 0;
static void ERRSVKWD(FileLine* fileline, const string& tokname) {
static int toldonce = 0;
fileline->v3error(string("Unexpected \"")+tokname+"\": \""+tokname+"\" is a SystemVerilog keyword misused as an identifier.");
if (!toldonce++) fileline->v3error("Modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.");
fileline->v3error(string("Unexpected \"")+tokname+"\": \""+tokname
+"\" is a SystemVerilog keyword misused as an identifier."
+(!toldonce++
? "\n"+V3Error::warnMore()
+"... Modify the Verilog-2001 code to avoid SV keywords,"
+" or use `begin_keywords or --language."
: ""));
}
//======================================================================

2
test_regress/t/t_array_list_bad.out
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@ -1,4 +1,4 @@
%Error: t/t_array_list_bad.v:37: Assignment pattern missed initializing elements: MEMBERDTYPE 't3'
%Warning-WIDTH: t/t_array_list_bad.v:37: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS's CONCAT generates 2 bits.
%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
%Error: Exiting due to

2
test_regress/t/t_assert_dup_bad.out
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@ -1,3 +1,3 @@
%Error: t/t_assert_dup_bad.v:16: Duplicate declaration of block: covlabel
%Error: t/t_assert_dup_bad.v:14: ... Location of original declaration
t/t_assert_dup_bad.v:14: ... Location of original declaration
%Error: Exiting due to

2
test_regress/t/t_cdc_async_bad.out
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@ -1,5 +1,5 @@
%Warning-CDCRSTLOGIC: t/t_cdc_async_bad.v:27: Logic in path that feeds async reset, via signal: t.rst2_bad_n
%Warning-CDCRSTLOGIC: Use "/* verilator lint_off CDCRSTLOGIC */" and lint_on around source to disable this message.
... Use "/* verilator lint_off CDCRSTLOGIC */" and lint_on around source to disable this message.
%Warning-CDCRSTLOGIC: See details in obj_vlt/t_cdc_async_bad/Vt_cdc_async_bad__cdc.txt
%Warning-CDCRSTLOGIC: t/t_cdc_async_bad.v:52: Logic in path that feeds async reset, via signal: t.rst6a_bad_n
%Warning-CDCRSTLOGIC: t/t_cdc_async_bad.v:53: Logic in path that feeds async reset, via signal: t.rst6b_bad_n

2
test_regress/t/t_clk_scope_bad.out
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@ -1,3 +1,3 @@
%Warning-CLKDATA: t/t_clk_scope_bad.v:35: Clock used as data (on rhs of assignment) in sequential block clk
%Warning-CLKDATA: Use "/* verilator lint_off CLKDATA */" and lint_on around source to disable this message.
... Use "/* verilator lint_off CLKDATA */" and lint_on around source to disable this message.
%Error: Exiting due to

2
test_regress/t/t_concat_large_bad.out
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@ -1,3 +1,3 @@
%Warning-WIDTHCONCAT: t/t_concat_large_bad.v:8: More than a 8k bit replication is probably wrong: 32768
%Warning-WIDTHCONCAT: Use "/* verilator lint_off WIDTHCONCAT */" and lint_on around source to disable this message.
... Use "/* verilator lint_off WIDTHCONCAT */" and lint_on around source to disable this message.
%Error: Exiting due to

2
test_regress/t/t_const_bad.out
View File

@ -1,5 +1,5 @@
%Warning-WIDTH: t/t_const_bad.v:12: Unsized constant being X/Z extended to 68 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
%Warning-WIDTH: t/t_const_bad.v:13: Unsized constant being X/Z extended to 68 bits: ?32?bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz
%Warning-WIDTH: t/t_const_bad.v:14: Unsized constant being X/Z extended to 68 bits: ?32?bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz
%Error: Exiting due to

2
test_regress/t/t_debug_fatalsrc_bad.pl
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@ -14,7 +14,7 @@ compile(
fails => $Self->{vlt_all},
expect =>
'%Error: Internal Error: .*: --debug-fatal-src
%Error: Internal Error: See the manual and http://www.veripool.org/verilator for more assistance.
.* See the manual and http://www.veripool.org/verilator for more assistance.
%Error: Command Failed.*',
);

2
test_regress/t/t_debug_fatalsrc_bt_bad.pl
View File

@ -15,7 +15,7 @@ compile(
fails => 1,
expect =>
'%Error: Internal Error: .*: --debug-fatal-src
%Error: Internal Error: See the manual and http://www.veripool.org/verilator for more assistance.
.*See the manual and http://www.veripool.org/verilator for more assistance.
.*in V3Options::.*
.*%Error: Command Failed.*',
);

2
test_regress/t/t_delay_stmtdly_bad.out
View File

@ -1,5 +1,5 @@
%Warning-ASSIGNDLY: t/t_delay.v:19: Unsupported: Ignoring delay on this assignment/primitive.
%Warning-ASSIGNDLY: Use "/* verilator lint_off ASSIGNDLY */" and lint_on around source to disable this message.
... Use "/* verilator lint_off ASSIGNDLY */" and lint_on around source to disable this message.
%Warning-ASSIGNDLY: t/t_delay.v:24: Unsupported: Ignoring delay on this assignment/primitive.
%Warning-ASSIGNDLY: t/t_delay.v:27: Unsupported: Ignoring delay on this assignment/primitive.
%Warning-STMTDLY: t/t_delay.v:33: Unsupported: Ignoring delay on this delayed statement.

4
test_regress/t/t_dpi_dup_bad.out
View File

@ -1,4 +1,4 @@
%Error: t/t_dpi_dup_bad.v:12: Duplicate declaration of DPI function with different formal arguments: t.oth_f_int2
%Error: t/t_dpi_dup_bad.v:12: ... New prototype: pure int dpii_fa_bit (int, int)
%Error: t/t_dpi_dup_bad.v:11: ... Original prototype: int dpii_fa_bit (int)
t/t_dpi_dup_bad.v:12: ... New prototype: pure int dpii_fa_bit (int, int)
t/t_dpi_dup_bad.v:11: ... Original prototype: int dpii_fa_bit (int)
%Error: Exiting due to

2
test_regress/t/t_enum_overlap_bad.out
View File

@ -1,3 +1,3 @@
%Error: t/t_enum_overlap_bad.v:11: Overlapping enumeration value: e1b
%Error: t/t_enum_overlap_bad.v:9: ... Location of original declaration
t/t_enum_overlap_bad.v:9: ... Location of original declaration
%Error: Exiting due to

9
test_regress/t/t_flag_topmodule.v
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@ -11,13 +11,20 @@ module a;
end
endmodule
module a2;
initial begin
$write("Bad top modules\n");
$stop;
end
endmodule
module b;
d d ();
endmodule
module c;
initial begin
$write("Bad top modules\n");
$write("Bad mid modules\n");
$stop;
end
endmodule

4
test_regress/t/t_flag_topmodule_bad.out Normal file
View File

@ -0,0 +1,4 @@
%Error-MULTITOP: t/t_flag_topmodule.v:14: Unsupported: Multiple top level modules: a2 and a
t/t_flag_topmodule.v:14: ... Fix, or use --top-module option to select which you want.
%Error-MULTITOP: t/t_flag_topmodule.v:21: Unsupported: Multiple top level modules: b and a2
%Error: Exiting due to

5
test_regress/t/t_flag_topmodule_bad.pl
View File

@ -14,10 +14,7 @@ top_filename("t/t_flag_topmodule.v");
compile(
fails => 1,
nc => 0, # Need to get it not to give the prompt
expect =>
'%Error-MULTITOP: t/t_flag_topmodule.v:\d+: Unsupported: Multiple top level modules: .*
%Error-MULTITOP: t/t_flag_topmodule.v:\d+: Fix, or use --top-module option to select which you want.
%Error: Exiting due to.*',
expect_filename => $Self->{golden_filename},
);
ok(1);

2
test_regress/t/t_flag_werror_bad1.out
View File

@ -1,3 +1,3 @@
%Warning-WIDTH: t/t_flag_werror.v:9: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's CONST '6'h2e' generates 6 bits.
%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
%Error: Exiting due to

2
test_regress/t/t_flag_wfatal.out
View File

@ -1,2 +1,2 @@
%Warning-WIDTH: t/t_flag_wfatal.v:9: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's CONST '6'h2e' generates 6 bits.
%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.

2
test_regress/t/t_func_bad_width.out
View File

@ -1,4 +1,4 @@
%Warning-WIDTH: t/t_func_bad_width.v:12: Operator FUNCREF 'MUX' expects 40 bits on the Function Argument, but Function Argument's VARREF 'in' generates 39 bits.
%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
%Warning-WIDTH: t/t_func_bad_width.v:12: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's FUNCREF 'MUX' generates 32 bits.
%Error: Exiting due to

20
test_regress/t/t_func_const2_bad.out
View File

@ -1,14 +1,12 @@
%Warning-USERFATAL: f_add = 15
%Warning-USERFATAL: Use "/* verilator lint_off USERFATAL */" and lint_on around source to disable this message.
... Use "/* verilator lint_off USERFATAL */" and lint_on around source to disable this message.
%Error: t/t_func_const2_bad.v:10: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_add2'
%Error: t/t_func_const2_bad.v:21: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing
Called from:
t/t_func_const2_bad.v:26: f_add() with parameters:
a = 32'h7
b = 32'h8
Called from:
t/t_func_const2_bad.v:10: f_add2() with parameters:
a = ?32?sh7
b = ?32?sh8
c = ?32?sh9
t/t_func_const2_bad.v:21: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing
t/t_func_const2_bad.v:26: ... Called from f_add() with parameters:
a = 32'h7
b = 32'h8
t/t_func_const2_bad.v:10: ... Called from f_add2() with parameters:
a = ?32?sh7
b = ?32?sh8
c = ?32?sh9
%Error: Exiting due to

39
test_regress/t/t_func_const_bad.out
View File

@ -1,33 +1,28 @@
%Error: t/t_func_const_bad.v:11: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_bad_output'
%Error: t/t_func_const_bad.v:12: ... Location of non-constant VAR 'o': Language violation: Outputs/refs not allowed in constant functions
t/t_func_const_bad.v:12: ... Location of non-constant VAR 'o': Language violation: Outputs/refs not allowed in constant functions
%Error: t/t_func_const_bad.v:20: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_bad_dotted'
%Error: t/t_func_const_bad.v:22: ... Location of non-constant VARXREF 'EIGHT': Language violation: Dotted hierarchical references not allowed in constant functions
Called from:
t/t_func_const_bad.v:20: f_bad_dotted() with parameters:
a = ?32?sh2
t/t_func_const_bad.v:22: ... Location of non-constant VARXREF 'EIGHT': Language violation: Dotted hierarchical references not allowed in constant functions
t/t_func_const_bad.v:20: ... Called from f_bad_dotted() with parameters:
a = ?32?sh2
%Error: t/t_func_const_bad.v:27: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_bad_nonparam'
%Error: t/t_func_const_bad.v:29: ... Location of non-constant VARREF 'modvar': Language violation: reference to non-function-local variable
Called from:
t/t_func_const_bad.v:27: f_bad_nonparam() with parameters:
a = ?32?sh3
t/t_func_const_bad.v:29: ... Location of non-constant VARREF 'modvar': Language violation: reference to non-function-local variable
t/t_func_const_bad.v:27: ... Called from f_bad_nonparam() with parameters:
a = ?32?sh3
%Error: t/t_func_const_bad.v:35: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_bad_infinite'
%Error: t/t_func_const_bad.v:37: ... Location of non-constant WHILE: Loop unrolling took too long; probably this is an infinite loop, or set --unroll-count above 1024
Called from:
t/t_func_const_bad.v:35: f_bad_infinite() with parameters:
a = ?32?sh3
t/t_func_const_bad.v:37: ... Location of non-constant WHILE: Loop unrolling took too long; probably this is an infinite loop, or set --unroll-count above 1024
t/t_func_const_bad.v:35: ... Called from f_bad_infinite() with parameters:
a = ?32?sh3
%Error: t/t_func_const_bad.v:43: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_bad_stop'
%Error: t/t_func_const_bad.v:45: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing
Called from:
t/t_func_const_bad.v:43: f_bad_stop() with parameters:
a = ?32?sh3
t/t_func_const_bad.v:45: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing
t/t_func_const_bad.v:43: ... Called from f_bad_stop() with parameters:
a = ?32?sh3
-Info: Printing in loop: 0
-Info: Printing in loop: 1
-Info: Printing in loop: 2
%Warning-USERFATAL: Fatal Error
%Warning-USERFATAL: Use "/* verilator lint_off USERFATAL */" and lint_on around source to disable this message.
... Use "/* verilator lint_off USERFATAL */" and lint_on around source to disable this message.
%Error: t/t_func_const_bad.v:49: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_bad_fatal'
%Error: t/t_func_const_bad.v:54: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing
Called from:
t/t_func_const_bad.v:49: f_bad_fatal() with parameters:
a = ?32?sh3
t/t_func_const_bad.v:54: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing
t/t_func_const_bad.v:49: ... Called from f_bad_fatal() with parameters:
a = ?32?sh3
%Error: Exiting due to

18
test_regress/t/t_func_const_packed_array_bad.out
View File

@ -1,13 +1,11 @@
%Warning-USERFATAL: f_add = 15
%Warning-USERFATAL: Use "/* verilator lint_off USERFATAL */" and lint_on around source to disable this message.
... Use "/* verilator lint_off USERFATAL */" and lint_on around source to disable this message.
%Error: t/t_func_const_packed_array_bad.v:11: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_add2'
%Error: t/t_func_const_packed_array_bad.v:22: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing
Called from:
t/t_func_const_packed_array_bad.v:30: f_add() with parameters:
params = [0 = 32'h7, 1 = 32'h8]
Called from:
t/t_func_const_packed_array_bad.v:11: f_add2() with parameters:
a = ?32?sh7
b = ?32?sh8
c = ?32?sh9
t/t_func_const_packed_array_bad.v:22: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing
t/t_func_const_packed_array_bad.v:30: ... Called from f_add() with parameters:
params = [0 = 32'h7, 1 = 32'h8]
t/t_func_const_packed_array_bad.v:11: ... Called from f_add2() with parameters:
a = ?32?sh7
b = ?32?sh8
c = ?32?sh9
%Error: Exiting due to

18
test_regress/t/t_func_const_packed_struct_bad.out
View File

@ -1,13 +1,11 @@
%Warning-USERFATAL: f_add = 15
%Warning-USERFATAL: Use "/* verilator lint_off USERFATAL */" and lint_on around source to disable this message.
... Use "/* verilator lint_off USERFATAL */" and lint_on around source to disable this message.
%Error: t/t_func_const_packed_struct_bad.v:13: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_add2'
%Error: t/t_func_const_packed_struct_bad.v:24: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing
Called from:
t/t_func_const_packed_struct_bad.v:32: f_add() with parameters:
params = [0 = '{a: 32'h7, b: 32'h22b}, 1 = '{a: 32'h3039, b: 32'h8}]
Called from:
t/t_func_const_packed_struct_bad.v:13: f_add2() with parameters:
a = ?32?sh7
b = ?32?sh8
c = ?32?sh9
t/t_func_const_packed_struct_bad.v:24: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing
t/t_func_const_packed_struct_bad.v:32: ... Called from f_add() with parameters:
params = [0 = '{a: 32'h7, b: 32'h22b}, 1 = '{a: 32'h3039, b: 32'h8}]
t/t_func_const_packed_struct_bad.v:13: ... Called from f_add2() with parameters:
a = ?32?sh7
b = ?32?sh8
c = ?32?sh9
%Error: Exiting due to

18
test_regress/t/t_func_const_packed_struct_bad2.out
View File

@ -1,13 +1,11 @@
%Warning-USERFATAL: f_add = 15
%Warning-USERFATAL: Use "/* verilator lint_off USERFATAL */" and lint_on around source to disable this message.
... Use "/* verilator lint_off USERFATAL */" and lint_on around source to disable this message.
%Error: t/t_func_const_packed_struct_bad2.v:19: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_add2'
%Error: t/t_func_const_packed_struct_bad2.v:30: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing
Called from:
t/t_func_const_packed_struct_bad2.v:42: f_add() with parameters:
params = [0 = '{a: 32'h7, foo: 6'hb, sub_params: '{b: 32'h37, bar: 8'h6f}}, 1 = '{a: 32'h3039, foo: 6'hc, sub_params: '{b: 32'h8, bar: 8'h70}}]
Called from:
t/t_func_const_packed_struct_bad2.v:19: f_add2() with parameters:
a = ?32?sh7
b = ?32?sh8
c = ?32?sh9
t/t_func_const_packed_struct_bad2.v:30: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing
t/t_func_const_packed_struct_bad2.v:42: ... Called from f_add() with parameters:
params = [0 = '{a: 32'h7, foo: 6'hb, sub_params: '{b: 32'h37, bar: 8'h6f}}, 1 = '{a: 32'h3039, foo: 6'hc, sub_params: '{b: 32'h8, bar: 8'h70}}]
t/t_func_const_packed_struct_bad2.v:19: ... Called from f_add2() with parameters:
a = ?32?sh7
b = ?32?sh8
c = ?32?sh9
%Error: Exiting due to

18
test_regress/t/t_func_const_struct_bad.out
View File

@ -1,13 +1,11 @@
%Warning-USERFATAL: f_add = 15
%Warning-USERFATAL: Use "/* verilator lint_off USERFATAL */" and lint_on around source to disable this message.
... Use "/* verilator lint_off USERFATAL */" and lint_on around source to disable this message.
%Error: t/t_func_const_struct_bad.v:16: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_add2'
%Error: t/t_func_const_struct_bad.v:27: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing
Called from:
t/t_func_const_struct_bad.v:37: f_add() with parameters:
params = '{a: 32'h7, b: 32'h8}
Called from:
t/t_func_const_struct_bad.v:16: f_add2() with parameters:
a = ?32?sh7
b = ?32?sh8
c = ?32?sh9
t/t_func_const_struct_bad.v:27: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing
t/t_func_const_struct_bad.v:37: ... Called from f_add() with parameters:
params = '{a: 32'h7, b: 32'h8}
t/t_func_const_struct_bad.v:16: ... Called from f_add2() with parameters:
a = ?32?sh7
b = ?32?sh8
c = ?32?sh9
%Error: Exiting due to

2
test_regress/t/t_func_void_bad.out
View File

@ -1,3 +1,3 @@
%Warning-IGNOREDRETURN: t/t_func_void_bad.v:25: Ignoring return value of non-void function (IEEE 2017 13.4.1)
%Warning-IGNOREDRETURN: Use "/* verilator lint_off IGNOREDRETURN */" and lint_on around source to disable this message.
... Use "/* verilator lint_off IGNOREDRETURN */" and lint_on around source to disable this message.
%Error: Exiting due to

2
test_regress/t/t_gen_cond_bitrange_bad.out
View File

@ -1,5 +1,5 @@
%Warning-SELRANGE: t/t_gen_cond_bitrange_bad.v:58: Selection index out of range: 2:2 outside 1:0
%Warning-SELRANGE: Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message.
... Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message.
%Warning-SELRANGE: t/t_gen_cond_bitrange_bad.v:70: Selection index out of range: 2:2 outside 1:0
%Warning-SELRANGE: t/t_gen_cond_bitrange_bad.v:83: Selection index out of range: 2:2 outside 1:0
%Warning-SELRANGE: t/t_gen_cond_bitrange_bad.v:96: Selection index out of range: 2:2 outside 1:0

32
test_regress/t/t_gen_missing_bad.out
View File

@ -1,18 +1,18 @@
%Error: t/t_gen_missing.v:42: Cannot find file containing module: foo_not_needed
%Error: t/t_gen_missing.v:42: Looked in:
%Error: t/t_gen_missing.v:42: t/foo_not_needed
%Error: t/t_gen_missing.v:42: t/foo_not_needed.v
%Error: t/t_gen_missing.v:42: t/foo_not_needed.sv
%Error: t/t_gen_missing.v:42: obj_dir//foo_not_needed
%Error: t/t_gen_missing.v:42: obj_dir//foo_not_needed.v
%Error: t/t_gen_missing.v:42: obj_dir//foo_not_needed.sv
%Error: t/t_gen_missing.v:42: ../include/foo_not_needed
%Error: t/t_gen_missing.v:42: ../include/foo_not_needed.v
%Error: t/t_gen_missing.v:42: ../include/foo_not_needed.sv
%Error: t/t_gen_missing.v:42: foo_not_needed
%Error: t/t_gen_missing.v:42: foo_not_needed.v
%Error: t/t_gen_missing.v:42: foo_not_needed.sv
%Error: t/t_gen_missing.v:42: obj_vlt/t_gen_missing_bad/foo_not_needed
%Error: t/t_gen_missing.v:42: obj_vlt/t_gen_missing_bad/foo_not_needed.v
%Error: t/t_gen_missing.v:42: obj_vlt/t_gen_missing_bad/foo_not_needed.sv
... Looked in:
t/foo_not_needed
t/foo_not_needed.v
t/foo_not_needed.sv
obj_dir//foo_not_needed
obj_dir//foo_not_needed.v
obj_dir//foo_not_needed.sv
../include/foo_not_needed
../include/foo_not_needed.v
../include/foo_not_needed.sv
foo_not_needed
foo_not_needed.v
foo_not_needed.sv
obj_vlt/t_gen_missing_bad/foo_not_needed
obj_vlt/t_gen_missing_bad/foo_not_needed.v
obj_vlt/t_gen_missing_bad/foo_not_needed.sv
%Error: Exiting due to

2
test_regress/t/t_hierarchy_identifier_bad.out
View File

@ -1,5 +1,5 @@
%Warning-ENDLABEL: t/t_hierarchy_identifier_bad.v:33: End label 'if_cnt_finish_bad' does not match begin label 'if_cnt_finish'
%Warning-ENDLABEL: Use "/* verilator lint_off ENDLABEL */" and lint_on around source to disable this message.
... Use "/* verilator lint_off ENDLABEL */" and lint_on around source to disable this message.
%Warning-ENDLABEL: t/t_hierarchy_identifier_bad.v:39: End label 'generate_for_bad' does not match begin label 'generate_for'
%Warning-ENDLABEL: t/t_hierarchy_identifier_bad.v:46: End label 'generate_if_if_bad' does not match begin label 'generate_if_if'
%Warning-ENDLABEL: t/t_hierarchy_identifier_bad.v:50: End label 'generate_if_else_bad' does not match begin label 'generate_if_else'

2
test_regress/t/t_inst_missing_bad.out
View File

@ -1,5 +1,5 @@
%Warning-PINNOCONNECT: t/t_inst_missing_bad.v:8: Cell pin is not connected: __pinNumber2
%Warning-PINNOCONNECT: Use "/* verilator lint_off PINNOCONNECT */" and lint_on around source to disable this message.
... Use "/* verilator lint_off PINNOCONNECT */" and lint_on around source to disable this message.
%Warning-PINCONNECTEMPTY: t/t_inst_missing_bad.v:8: Cell pin connected by name with empty reference: nc
%Warning-PINMISSING: t/t_inst_missing_bad.v:8: Cell has missing pin: missing
%Error: Exiting due to

2
test_regress/t/t_inst_overwide_bad.out
View File

@ -1,5 +1,5 @@
%Warning-WIDTH: t/t_inst_overwide.v:22: Output port connection 'outy_w92' expects 92 bits on the pin connection, but pin connection's VARREF 'outc_w30' generates 30 bits.
%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
%Warning-WIDTH: t/t_inst_overwide.v:23: Output port connection 'outz_w22' expects 22 bits on the pin connection, but pin connection's VARREF 'outd_w73' generates 73 bits.
%Warning-WIDTH: t/t_inst_overwide.v:26: Input port connection 'inw_w31' expects 31 bits on the pin connection, but pin connection's VARREF 'ina_w1' generates 1 bits.
%Warning-WIDTH: t/t_inst_overwide.v:27: Input port connection 'inx_w11' expects 11 bits on the pin connection, but pin connection's VARREF 'inb_w61' generates 61 bits.

3
test_regress/t/t_inst_recurse_bad.out Normal file
View File

@ -0,0 +1,3 @@
%Error: t/t_inst_recurse_bad.v:17: Unsupported: Recursive multiple modules (module instantiates something leading back to itself): looped
... Note self-recursion (module instantiating itself directly) is supported.
%Error: Exiting due to

5
test_regress/t/t_inst_recurse_bad.pl
View File

@ -11,10 +11,7 @@ scenarios(simulator => 1);
compile(
fails => 1,
expect =>
'.*%Error: t/t_inst_recurse_bad.v:\d+: Unsupported: Recursive multiple modules \(module instantiates something leading back to itself\): looped
%Error: t/t_inst_recurse_bad.v:\d+: Note self-recursion \(module instantiating itself directly\) is supported.
%Error: Exiting due to.*',
expect_filename => $Self->{golden_filename},
);
ok(1);

2
test_regress/t/t_interface_array_nocolon_bad.out
View File

@ -1,5 +1,5 @@
%Warning-LITENDIAN: t/t_interface_array_nocolon_bad.v:25: Little endian cell range connecting to vector: MSB < LSB of cell range: 0:2
%Warning-LITENDIAN: Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.
... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.
%Warning-LITENDIAN: t/t_interface_array_nocolon_bad.v:26: Little endian cell range connecting to vector: MSB < LSB of cell range: 1:3
%Warning-LITENDIAN: t/t_interface_array_nocolon_bad.v:29: Little endian cell range connecting to vector: MSB < LSB of cell range: 0:2
%Warning-LITENDIAN: t/t_interface_array_nocolon_bad.v:30: Little endian cell range connecting to vector: MSB < LSB of cell range: 1:3

2
test_regress/t/t_interface_mismodport_bad.out
View File

@ -1,3 +1,3 @@
%Error: t/t_interface_mismodport_bad.v:35: Can't find definition of 'bad' in dotted signal: isub.bad
%Error: Known scopes under 'bad': <no cells found>
... Known scopes under 'bad': <no cells found>
%Error: Exiting due to

2
test_regress/t/t_lint_always_comb_bad.out
View File

@ -1,6 +1,6 @@
%Error-PROCASSWIRE: t/t_lint_always_comb_bad.v:28: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): temp1
%Error-PROCASSWIRE: t/t_lint_always_comb_bad.v:30: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): temp1
%Warning-ALWCOMBORDER: t/t_lint_always_comb_bad.v:31: Always_comb variable driven after use: mid
%Warning-ALWCOMBORDER: Use "/* verilator lint_off ALWCOMBORDER */" and lint_on around source to disable this message.
... Use "/* verilator lint_off ALWCOMBORDER */" and lint_on around source to disable this message.
%Error-PROCASSWIRE: t/t_lint_always_comb_bad.v:45: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): temp1_d1r
%Error: Exiting due to

6
test_regress/t/t_lint_blksync_bad.out
View File

@ -1,6 +1,6 @@
%Warning-BLKSEQ: t/t_lint_blksync_bad.v:23: Blocking assignments (=) in sequential (flop or latch) block; suggest delayed assignments (<=).
%Warning-BLKSEQ: Use "/* verilator lint_off BLKSEQ */" and lint_on around source to disable this message.
... Use "/* verilator lint_off BLKSEQ */" and lint_on around source to disable this message.
%Warning-COMBDLY: t/t_lint_blksync_bad.v:30: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).
%Warning-COMBDLY: *** See the manual before disabling this,
%Warning-COMBDLY: else you may end up with different sim results.
*** See the manual before disabling this,
else you may end up with different sim results.
%Error: Exiting due to

3
test_regress/t/t_lint_colonplus_bad.out Normal file
View File

@ -0,0 +1,3 @@
%Warning-COLONPLUS: t/t_lint_colonplus_bad.v:12: Perhaps instead of ':+' the intent was '+:'?
... Use "/* verilator lint_off COLONPLUS */" and lint_on around source to disable this message.
%Error: Exiting due to

5
test_regress/t/t_lint_colonplus_bad.pl
View File

@ -15,10 +15,7 @@ compile(
make_top_shell => 0,
make_main => 0,
fails => 1,
expect =>
q{%Warning-COLONPLUS: t/t_lint_colonplus_bad.v:\d+: Perhaps instead of ':\+' the intent was '\+:'\?
%Warning-COLONPLUS: Use .*
.*%Error: Exiting due to.*},
expect_filename => $Self->{golden_filename},
);
ok(1);

3
test_regress/t/t_lint_declfilename_bad.out Normal file
View File

@ -0,0 +1,3 @@
%Warning-DECLFILENAME: t/t_lint_declfilename.v:6: Filename 't_lint_declfilename' does not match MODULE name: t
... Use "/* verilator lint_off DECLFILENAME */" and lint_on around source to disable this message.
%Error: Exiting due to

7
test_regress/t/t_lint_declfilename_bad.pl
View File

@ -7,7 +7,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
scenarios(vlt_all => 1);
scenarios(vlt => 1);
top_filename("t/t_lint_declfilename.v");
@ -17,10 +17,7 @@ compile(
verilator_make_gcc => 0,
make_top_shell => 0,
make_main => 0,
expect =>
'%Warning-DECLFILENAME: t/t_lint_declfilename.v:6: Filename \'t_lint_declfilename\' does not match MODULE name: t
%Warning-DECLFILENAME: Use .* to disable this message.
%Error: Exiting due to.*',
expect_filename => $Self->{golden_filename},
);
ok(1);

3
test_regress/t/t_lint_defparam_bad.out Normal file
View File

@ -0,0 +1,3 @@
%Warning-DEFPARAM: t/t_lint_defparam.v:9: Suggest replace defparam with Verilog 2001 #(.P(...etc...))
... Use "/* verilator lint_off DEFPARAM */" and lint_on around source to disable this message.
%Error: Exiting due to

7
test_regress/t/t_lint_defparam_bad.pl
View File

@ -7,7 +7,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
scenarios(vlt_all => 1);
scenarios(vlt => 1);
top_filename("t/t_lint_defparam.v");
@ -17,10 +17,7 @@ compile(
verilator_make_gcc => 0,
make_top_shell => 0,
make_main => 0,
expect =>
'%Warning-DEFPARAM: t/t_lint_defparam.v:\d+: Suggest replace defparam with Verilog 2001 #\(.P\(...etc...\)\)
%Warning-DEFPARAM: Use .* to disable this message.
%Error: Exiting due to.*',
expect_filename => $Self->{golden_filename},
);
ok(1);

2
test_regress/t/t_lint_ifdepth_bad.out
View File

@ -1,3 +1,3 @@
%Warning-IFDEPTH: t/t_lint_ifdepth_bad.v:21: Deep 'if' statement; suggest unique/priority to avoid slow logic
%Warning-IFDEPTH: Use "/* verilator lint_off IFDEPTH */" and lint_on around source to disable this message.
... Use "/* verilator lint_off IFDEPTH */" and lint_on around source to disable this message.
%Error: Exiting due to

2
test_regress/t/t_lint_implicit_bad.out
View File

@ -1,5 +1,5 @@
%Warning-IMPLICIT: t/t_lint_implicit.v:10: Signal definition not found, creating implicitly: b
%Warning-IMPLICIT: Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.
... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.
%Warning-IMPLICIT: t/t_lint_implicit.v:12: Signal definition not found, creating implicitly: nt0
%Warning-IMPLICIT: t/t_lint_implicit.v:15: Signal definition not found, creating implicitly: dummy1
%Warning-IMPLICIT: t/t_lint_implicit.v:15: Signal definition not found, creating implicitly: dummy2

2
test_regress/t/t_lint_implicit_def_bad.out
View File

@ -1,4 +1,4 @@
%Warning-IMPLICIT: t/t_lint_implicit_def_bad.v:10: Signal definition not found, creating implicitly: imp_warn
%Warning-IMPLICIT: Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.
... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.
%Error: t/t_lint_implicit_def_bad.v:15: Signal definition not found, and implicit disabled with `default_nettype: imp_err
%Error: Exiting due to

2
test_regress/t/t_lint_importstar_bad.out
View File

@ -1,3 +1,3 @@
%Warning-IMPORTSTAR: t/t_lint_importstar_bad.v:10: Import::* in $unit scope may pollute global namespace
%Warning-IMPORTSTAR: Use "/* verilator lint_off IMPORTSTAR */" and lint_on around source to disable this message.
... Use "/* verilator lint_off IMPORTSTAR */" and lint_on around source to disable this message.
%Error: Exiting due to

3
test_regress/t/t_lint_incabspath_bad.out Normal file
View File

@ -0,0 +1,3 @@
%Warning-INCABSPATH: t/t_lint_incabspath.v:6: Suggest `include with absolute path be made relative, and use +include: /dev/null
... Use "/* verilator lint_off INCABSPATH */" and lint_on around source to disable this message.
%Error: Exiting due to

7
test_regress/t/t_lint_incabspath_bad.pl
View File

@ -7,7 +7,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
scenarios(vlt_all => 1);
scenarios(vlt => 1);
top_filename("t/t_lint_incabspath.v");
@ -17,10 +17,7 @@ compile(
verilator_make_gcc => 0,
make_top_shell => 0,
make_main => 0,
expect =>
'%Warning-INCABSPATH: t/t_lint_incabspath.v:\d+: Suggest `include with absolute path be made relative, and use \+include: /dev/null
%Warning-INCABSPATH: Use .* to disable this message.
%Error: Exiting due to.*',
expect_filename => $Self->{golden_filename},
);
ok(1);

2
test_regress/t/t_lint_infinite.out
View File

@ -1,4 +1,4 @@
%Warning-INFINITELOOP: t/t_lint_infinite.v:9: Infinite loop (condition always true)
%Warning-INFINITELOOP: Use "/* verilator lint_off INFINITELOOP */" and lint_on around source to disable this message.
... Use "/* verilator lint_off INFINITELOOP */" and lint_on around source to disable this message.
%Warning-INFINITELOOP: t/t_lint_infinite.v:11: Infinite loop (condition always true)
%Error: Exiting due to

6
test_regress/t/t_lint_latch_bad.out
View File

@ -1,5 +1,5 @@
%Warning-COMBDLY: t/t_lint_latch_bad.v:24: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).
%Warning-COMBDLY: Use "/* verilator lint_off COMBDLY */" and lint_on around source to disable this message.
%Warning-COMBDLY: *** See the manual before disabling this,
%Warning-COMBDLY: else you may end up with different sim results.
... Use "/* verilator lint_off COMBDLY */" and lint_on around source to disable this message.
*** See the manual before disabling this,
else you may end up with different sim results.
%Error: Exiting due to

10
test_regress/t/t_lint_multidriven_bad.out
View File

@ -1,8 +1,8 @@
%Warning-MULTIDRIVEN: t/t_lint_multidriven_bad.v:20: Signal has multiple driving blocks with different clocking: t.mem
%Warning-MULTIDRIVEN: t/t_lint_multidriven_bad.v:26: ... Location of first driving block
%Warning-MULTIDRIVEN: t/t_lint_multidriven_bad.v:23: ... Location of other driving block
%Warning-MULTIDRIVEN: Use "/* verilator lint_off MULTIDRIVEN */" and lint_on around source to disable this message.
t/t_lint_multidriven_bad.v:26: ... Location of first driving block
t/t_lint_multidriven_bad.v:23: ... Location of other driving block
... Use "/* verilator lint_off MULTIDRIVEN */" and lint_on around source to disable this message.
%Warning-MULTIDRIVEN: t/t_lint_multidriven_bad.v:18: Signal has multiple driving blocks with different clocking: out2
%Warning-MULTIDRIVEN: t/t_lint_multidriven_bad.v:34: ... Location of first driving block
%Warning-MULTIDRIVEN: t/t_lint_multidriven_bad.v:31: ... Location of other driving block
t/t_lint_multidriven_bad.v:34: ... Location of first driving block
t/t_lint_multidriven_bad.v:31: ... Location of other driving block
%Error: Exiting due to

2
test_regress/t/t_lint_once_bad.out
View File

@ -1,4 +1,4 @@
%Warning-UNUSED: t/t_lint_once_bad.v:18: Signal is not driven, nor used: unus1
%Warning-UNUSED: Use "/* verilator lint_off UNUSED */" and lint_on around source to disable this message.
... Use "/* verilator lint_off UNUSED */" and lint_on around source to disable this message.
%Warning-UNUSED: t/t_lint_once_bad.v:18: Signal is not driven, nor used: unus2
%Error: Exiting due to

4
test_regress/t/t_lint_pindup_bad.out
View File

@ -1,6 +1,6 @@
%Error: t/t_lint_pindup_bad.v:17: Duplicate pin connection: i
%Error: t/t_lint_pindup_bad.v:16: ... Location of original pin connection
t/t_lint_pindup_bad.v:16: ... Location of original pin connection
%Error: t/t_lint_pindup_bad.v:18: Pin not found: __pinNumber4
%Error: t/t_lint_pindup_bad.v:14: Duplicate parameter pin connection: P
%Error: t/t_lint_pindup_bad.v:14: ... Location of original parameter pin connection
t/t_lint_pindup_bad.v:14: ... Location of original parameter pin connection
%Error: Exiting due to

2
test_regress/t/t_lint_pkg_colon_bad.out
View File

@ -1,4 +1,4 @@
%Error: t/t_lint_pkg_colon_bad.v:6: syntax error, unexpected ::, expecting ')' or ','
%Error: t/t_lint_pkg_colon_bad.v:6: Perhaps 'mispkg' is a package which needs to be predeclared? (IEEE 2017 26.3)
t/t_lint_pkg_colon_bad.v:6: ... Perhaps 'mispkg' is a package which needs to be predeclared? (IEEE 2017 26.3)
%Error: t/t_lint_pkg_colon_bad.v:7: syntax error, unexpected ::, expecting ',' or ';'
%Error: Exiting due to

3
test_regress/t/t_lint_realcvt_bad.out Normal file
View File

@ -0,0 +1,3 @@
%Warning-REALCVT: t/t_lint_realcvt_bad.v:9: Implicit conversion of real to integer
... Use "/* verilator lint_off REALCVT */" and lint_on around source to disable this message.
%Error: Exiting due to

7
test_regress/t/t_lint_realcvt_bad.pl
View File

@ -7,7 +7,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
scenarios(vlt_all => 1);
scenarios(vlt => 1);
compile(
v_flags2 => ["--lint-only -Wwarn-REALCVT"],
@ -15,10 +15,7 @@ compile(
make_top_shell => 0,
make_main => 0,
fails => 1,
expect =>
'%Warning-REALCVT: t/t_lint_realcvt_bad.v:\d+: Implicit conversion of real to integer
%Warning-REALCVT: Use .* to disable this message.
%Error: Exiting due to.*',
expect_filename => $Self->{golden_filename},
);
ok(1);

2
test_regress/t/t_lint_repeat_bad.out
View File

@ -1,3 +1,3 @@
%Warning-WIDTH: t/t_lint_repeat_bad.v:17: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS's VARREF 'a' generates 2 bits.
%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
%Error: Exiting due to

2
test_regress/t/t_lint_restore_bad.out
View File

@ -1,3 +1,3 @@
%Warning-WIDTH: t/t_lint_restore_bad.v:18: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS's CONST '64'h1' generates 64 bits.
%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
%Error: Exiting due to

6
test_regress/t/t_lint_syncasyncnet_bad.out
View File

@ -1,5 +1,5 @@
%Warning-SYNCASYNCNET: t/t_lint_syncasyncnet_bad.v:15: Signal flopped as both synchronous and async: rst_both_l
%Warning-SYNCASYNCNET: t/t_lint_syncasyncnet_bad.v:90: ... Location of async usage
%Warning-SYNCASYNCNET: t/t_lint_syncasyncnet_bad.v:58: ... Location of sync usage
%Warning-SYNCASYNCNET: Use "/* verilator lint_off SYNCASYNCNET */" and lint_on around source to disable this message.
t/t_lint_syncasyncnet_bad.v:90: ... Location of async usage
t/t_lint_syncasyncnet_bad.v:58: ... Location of sync usage
... Use "/* verilator lint_off SYNCASYNCNET */" and lint_on around source to disable this message.
%Error: Exiting due to

3
test_regress/t/t_lint_unsized_bad.out
View File

@ -1,3 +1,4 @@
%Error: t/t_lint_unsized_bad.v:7: Too many digits for 32 bit number: 'd123456789123456789123456789
%Error: t/t_lint_unsized_bad.v:7: As that number was unsized ('d...) it is limited to 32 bits (IEEE 2017 5.7.1)
... As that number was unsized ('d...) it is limited to 32 bits (IEEE 2017 5.7.1)
... Suggest adding a size to it.
%Error: Exiting due to

2
test_regress/t/t_lint_unused_bad.out
View File

@ -1,5 +1,5 @@
%Warning-UNUSED: t/t_lint_unused_bad.v:16: Bits of signal are not used: assunu1[5:1]
%Warning-UNUSED: Use "/* verilator lint_off UNUSED */" and lint_on around source to disable this message.
... Use "/* verilator lint_off UNUSED */" and lint_on around source to disable this message.
%Warning-UNDRIVEN: t/t_lint_unused_bad.v:20: Bits of signal are not driven: udrb2[14:13,11]
%Warning-UNUSED: t/t_lint_unused_bad.v:25: Signal is not driven, nor used: unu3
%Warning-UNUSED: t/t_lint_unused_bad.v:27: Bits of signal are not driven, nor used: mixed[3]

2
test_regress/t/t_lint_unused_iface_bad.out
View File

@ -1,4 +1,4 @@
%Warning-UNDRIVEN: t/t_lint_unused_iface_bad.v:7: Signal is not driven: sig_udrv
%Warning-UNDRIVEN: Use "/* verilator lint_off UNDRIVEN */" and lint_on around source to disable this message.
... Use "/* verilator lint_off UNDRIVEN */" and lint_on around source to disable this message.
%Warning-UNUSED: t/t_lint_unused_iface_bad.v:8: Signal is not used: sig_uusd
%Error: Exiting due to

2
test_regress/t/t_lint_width_bad.out
View File

@ -1,5 +1,5 @@
%Warning-WIDTH: t/t_lint_width_bad.v:16: Operator VAR 'XS' expects 4 bits on the Initial value, but Initial value's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.
%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
%Warning-WIDTH: t/t_lint_width_bad.v:38: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'in' generates 4 bits.
%Warning-WIDTH: t/t_lint_width_bad.v:20: Operator SHIFTL expects 5 bits on the LHS, but LHS's CONST '1'h1' generates 1 bits.
%Warning-WIDTH: t/t_lint_width_bad.v:26: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS's SHIFTL generates 7 bits.

2
test_regress/t/t_mem_multi_ref_bad.out
View File

@ -2,7 +2,7 @@
%Error: t/t_mem_multi_ref_bad.v:14: Extracting 2 bits from only 1 bit number
%Error: t/t_mem_multi_ref_bad.v:15: Illegal bit or array select; type does not have a bit range, or bad dimension: type is logic
%Warning-SELRANGE: t/t_mem_multi_ref_bad.v:15: Selection index out of range: 1:1 outside 0:0
%Warning-SELRANGE: Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message.
... Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message.
%Error: t/t_mem_multi_ref_bad.v:16: Illegal bit or array select; type does not have a bit range, or bad dimension: type is logic
%Warning-SELRANGE: t/t_mem_multi_ref_bad.v:16: Selection index out of range: 1:1 outside 0:0
%Error: t/t_mem_multi_ref_bad.v:18: Illegal +: or -: select; type already selected, or bad dimension: type is UNPACKARRAYDTYPE

2
test_regress/t/t_metacmt_onoff.out
View File

@ -1,4 +1,4 @@
%Warning-LITENDIAN: t/t_metacmt_onoff.v:5: Little bit endian vector: MSB < LSB of bit range: 0:1
%Warning-LITENDIAN: Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.
... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.
%Warning-LITENDIAN: t/t_metacmt_onoff.v:5: Little bit endian vector: MSB < LSB of bit range: 0:3
%Error: Exiting due to

6
test_regress/t/t_mod_dup_bad.out Normal file
View File

@ -0,0 +1,6 @@
%Warning-MODDUP: t/t_mod_dup_bad.v:13: Duplicate declaration of module: a
t/t_mod_dup_bad.v:6: ... Location of original declaration
... Use "/* verilator lint_off MODDUP */" and lint_on around source to disable this message.
%Error-MULTITOP: t/t_mod_dup_bad.v:16: Unsupported: Multiple top level modules: b and test
t/t_mod_dup_bad.v:16: ... Fix, or use --top-module option to select which you want.
%Error: Exiting due to

8
test_regress/t/t_mod_dup_bad.pl
View File

@ -7,15 +7,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
scenarios(vlt_all => 1);
scenarios(vlt => 1);
compile(
fails => 1,
expect =>
'%Warning-MODDUP: t/t_mod_dup_bad.v:\d+: Duplicate declaration of module: a
%Warning-MODDUP: t/t_mod_dup_bad.v:\d+: ... Location of original declaration
.*
%Error: Exiting due to.*',
expect_filename => $Self->{golden_filename},
);
ok(1);

6
test_regress/t/t_order_loop_bad.pl
View File

@ -17,9 +17,9 @@ compile(
make_main => 0,
expect =>
'%Error: Circular logic when ordering code .*
%Error: Example path: t/t_order_loop_bad.v:\d+: ALWAYS
%Error: Example path: t/t_order_loop_bad.v:\d+: t.ready
%Error: Example path: t/t_order_loop_bad.v:\d+: ACTIVE
*t/t_order_loop_bad.v:\d+: + Example path: ALWAYS
*t/t_order_loop_bad.v:\d+: + Example path: t.ready
*t/t_order_loop_bad.v:\d+: + Example path: ACTIVE
.*',
);

2
test_regress/t/t_param_concat_bad.out
View File

@ -1,5 +1,5 @@
%Warning-WIDTHCONCAT: t/t_param_concat.v:18: Unsized numbers/parameters not allowed in concatenations.
%Warning-WIDTHCONCAT: Use "/* verilator lint_off WIDTHCONCAT */" and lint_on around source to disable this message.
... Use "/* verilator lint_off WIDTHCONCAT */" and lint_on around source to disable this message.
%Warning-WIDTHCONCAT: t/t_param_concat.v:18: Unsized numbers/parameters not allowed in replications.
%Warning-WIDTHCONCAT: t/t_param_concat.v:19: Unsized numbers/parameters not allowed in replications.
%Error: Exiting due to

2
test_regress/t/t_param_scope_bad.out
View File

@ -1,3 +1,3 @@
%Warning-CASEOVERLAP: t/t_param_scope_bad.v:27: Case values overlap (example pattern 0x2)
%Warning-CASEOVERLAP: Use "/* verilator lint_off CASEOVERLAP */" and lint_on around source to disable this message.
... Use "/* verilator lint_off CASEOVERLAP */" and lint_on around source to disable this message.
%Error: Exiting due to

2
test_regress/t/t_param_sel_range_bad.out
View File

@ -1,3 +1,3 @@
%Warning-SELRANGE: t/t_param_sel_range.v:40: Selection index out of range: 7:7 outside 4:0
%Warning-SELRANGE: Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message.
... Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message.
%Error: Exiting due to

2
test_regress/t/t_past_bad.out
View File

@ -1,4 +1,4 @@
%Error: t/t_past_bad.v:11: $past tick value must be constant and >= 1 (IEEE 2017 16.9.3)
%Warning-TICKCOUNT: t/t_past_bad.v:12: $past tick value of 10000 may have a large performance cost
%Warning-TICKCOUNT: Use "/* verilator lint_off TICKCOUNT */" and lint_on around source to disable this message.
... Use "/* verilator lint_off TICKCOUNT */" and lint_on around source to disable this message.
%Error: Exiting due to

2
test_regress/t/t_pp_dupdef_bad.out
View File

@ -1,5 +1,5 @@
%Warning-REDEFMACRO: t/t_pp_dupdef.v:10: Redefining existing define: DUP, with different value: barney
%Warning-REDEFMACRO: Use "/* verilator lint_off REDEFMACRO */" and lint_on around source to disable this message.
... Use "/* verilator lint_off REDEFMACRO */" and lint_on around source to disable this message.
%Warning-REDEFMACRO: t/t_pp_dupdef.v:10: Previous definition is here, with value: fred
%Warning-REDEFMACRO: t/t_pp_dupdef.v:13: Redefining existing define: DUPP, with different value: paramed(x,z) (x*z)
%Warning-REDEFMACRO: t/t_pp_dupdef.v:13: Previous definition is here, with value: paramed(x) (x)

2
test_regress/t/t_select_bad_range.out
View File

@ -1,4 +1,4 @@
%Warning-SELRANGE: t/t_select_bad_range.v:15: Selection index out of range: 44:44 outside 43:0
%Warning-SELRANGE: Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message.
... Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message.
%Warning-SELRANGE: t/t_select_bad_range.v:16: Selection index out of range: 44:41 outside 43:0
%Error: Exiting due to

2
test_regress/t/t_select_bad_range2.out
View File

@ -1,3 +1,3 @@
%Warning-SELRANGE: t/t_select_bad_range2.v:50: Selection index out of range: 3:2 outside 1:0
%Warning-SELRANGE: Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message.
... Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message.
%Error: Exiting due to

2
test_regress/t/t_select_bad_range3.out
View File

@ -1,3 +1,3 @@
%Warning-SELRANGE: t/t_select_bad_range3.v:18: Selection index out of range: 13 outside 12:10
%Warning-SELRANGE: Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message.
... Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message.
%Error: Exiting due to

3
test_regress/t/t_struct_unpacked_bad.out Normal file
View File

@ -0,0 +1,3 @@
%Warning-UNPACKED: t/t_struct_unpacked_bad.v:8: Unsupported: Unpacked struct/union
... Use "/* verilator lint_off UNPACKED */" and lint_on around source to disable this message.
%Error: Exiting due to

5
test_regress/t/t_struct_unpacked_bad.pl
View File

@ -11,10 +11,7 @@ scenarios(simulator => 1);
compile(
fails => $Self->{vlt_all},
expect =>
q{%Warning-UNPACKED: t/t_struct_unpacked_bad.v:\d+: Unsupported: Unpacked struct/union
%Warning-UNPACKED: Use .*
.*%Error: Exiting due to.*},
expect_filename => $Self->{golden_filename},
);
ok(1);

2
test_regress/t/t_tri_pull2_bad.out
View File

@ -1,3 +1,3 @@
%Error: t/t_tri_pull2_bad.v:9: Unsupported: Conflicting pull directions.
%Error: t/t_tri_pull2_bad.v:19: ... Location of conflicting pull.
t/t_tri_pull2_bad.v:19: ... Location of conflicting pull.
%Error: Exiting due to

2
test_regress/t/t_tri_pull_bad.out
View File

@ -1,3 +1,3 @@
%Error: t/t_tri_pull_bad.v:10: Unsupported: Conflicting pull directions.
%Error: t/t_tri_pull_bad.v:9: ... Location of conflicting pull.
t/t_tri_pull_bad.v:9: ... Location of conflicting pull.
%Error: Exiting due to

3
test_regress/t/t_tri_pullvec_bad.out
View File

@ -1,4 +1,5 @@
%Error: t/t_tri_pullvec_bad.v:10: Unsupported: Conflicting pull directions.
%Error: t/t_tri_pullvec_bad.v:9: ... Location of conflicting pull.
t/t_tri_pullvec_bad.v:9: ... Location of conflicting pull.
%Error: t/t_tri_pullvec_bad.v:11: Unsupported: Conflicting pull directions.
t/t_tri_pullvec_bad.v:9: ... Location of conflicting pull.
%Error: Exiting due to

12
test_regress/t/t_unopt_combo_bad.out
View File

@ -1,8 +1,8 @@
%Warning-UNOPTFLAT: t/t_unopt_combo.v:23: Signal unoptimizable: Feedback to clock or circular logic: t.c
%Warning-UNOPTFLAT: Use "/* verilator lint_off UNOPTFLAT */" and lint_on around source to disable this message.
%Warning-UNOPTFLAT: Example path: t/t_unopt_combo.v:23: t.c
%Warning-UNOPTFLAT: Example path: t/t_unopt_combo.v:80: ALWAYS
%Warning-UNOPTFLAT: Example path: t/t_unopt_combo.v:22: t.b
%Warning-UNOPTFLAT: Example path: t/t_unopt_combo.v:116: ALWAYS
%Warning-UNOPTFLAT: Example path: t/t_unopt_combo.v:23: t.c
... Use "/* verilator lint_off UNOPTFLAT */" and lint_on around source to disable this message.
t/t_unopt_combo.v:23: Example path: t.c
t/t_unopt_combo.v:80: Example path: ALWAYS
t/t_unopt_combo.v:22: Example path: t.b
t/t_unopt_combo.v:116: Example path: ALWAYS
t/t_unopt_combo.v:23: Example path: t.c
%Error: Exiting due to

8
test_regress/t/t_unopt_converge_unopt_bad.out
View File

@ -1,6 +1,6 @@
%Warning-UNOPT: t/t_unopt_converge.v:18: Signal unoptimizable: Feedback to public clock or circular logic: x
%Warning-UNOPT: Use "/* verilator lint_off UNOPT */" and lint_on around source to disable this message.
%Warning-UNOPT: Example path: t/t_unopt_converge.v:18: x
%Warning-UNOPT: Example path: t/t_unopt_converge.v:21: ALWAYS
%Warning-UNOPT: Example path: t/t_unopt_converge.v:18: x
... Use "/* verilator lint_off UNOPT */" and lint_on around source to disable this message.
t/t_unopt_converge.v:18: Example path: x
t/t_unopt_converge.v:21: Example path: ALWAYS
t/t_unopt_converge.v:18: Example path: x
%Error: Exiting due to

8
test_regress/t/t_unoptflat_simple_2_bad.out
View File

@ -1,8 +1,8 @@
%Warning-UNOPTFLAT: t/t_unoptflat_simple_2.v:14: Signal unoptimizable: Feedback to clock or circular logic: t.x
%Warning-UNOPTFLAT: Use "/* verilator lint_off UNOPTFLAT */" and lint_on around source to disable this message.
%Warning-UNOPTFLAT: Example path: t/t_unoptflat_simple_2.v:14: t.x
%Warning-UNOPTFLAT: Example path: t/t_unoptflat_simple_2.v:16: ASSIGNW
%Warning-UNOPTFLAT: Example path: t/t_unoptflat_simple_2.v:14: t.x
... Use "/* verilator lint_off UNOPTFLAT */" and lint_on around source to disable this message.
t/t_unoptflat_simple_2.v:14: Example path: t.x
t/t_unoptflat_simple_2.v:16: Example path: ASSIGNW
t/t_unoptflat_simple_2.v:14: Example path: t.x
%Warning-UNOPTFLAT: Widest candidate vars to split:
%Warning-UNOPTFLAT: t/t_unoptflat_simple_2.v:14: t.x, width 3, fanout 12
%Warning-UNOPTFLAT: Most fanned out candidate vars to split:

6
test_regress/t/t_var_bad_hide.out
View File

@ -1,6 +1,6 @@
%Warning-VARHIDDEN: t/t_var_bad_hide.v:15: Declaration of signal hides declaration in upper scope: top
%Warning-VARHIDDEN: t/t_var_bad_hide.v:12: ... Location of original declaration
%Warning-VARHIDDEN: Use "/* verilator lint_off VARHIDDEN */" and lint_on around source to disable this message.
t/t_var_bad_hide.v:12: ... Location of original declaration
... Use "/* verilator lint_off VARHIDDEN */" and lint_on around source to disable this message.
%Warning-VARHIDDEN: t/t_var_bad_hide.v:21: Declaration of signal hides declaration in upper scope: top
%Warning-VARHIDDEN: t/t_var_bad_hide.v:12: ... Location of original declaration
t/t_var_bad_hide.v:12: ... Location of original declaration
%Error: Exiting due to

4
test_regress/t/t_var_bad_hide2.out
View File

@ -1,4 +1,4 @@
%Warning-VARHIDDEN: t/t_var_bad_hide2.v:13: Declaration of signal hides declaration in upper scope: t
%Warning-VARHIDDEN: t/t_var_bad_hide2.v:6: ... Location of original declaration
%Warning-VARHIDDEN: Use "/* verilator lint_off VARHIDDEN */" and lint_on around source to disable this message.
t/t_var_bad_hide2.v:6: ... Location of original declaration
... Use "/* verilator lint_off VARHIDDEN */" and lint_on around source to disable this message.
%Error: Exiting due to

8
test_regress/t/t_var_bad_sameas.out
View File

@ -1,11 +1,11 @@
%Error: t/t_var_bad_sameas.v:9: Unsupported in C: Cell has the same name as variable: varfirst
%Error: t/t_var_bad_sameas.v:8: ... Location of original declaration
t/t_var_bad_sameas.v:8: ... Location of original declaration
%Error: t/t_var_bad_sameas.v:10: Unsupported in C: Task has the same name as cell: varfirst
%Error: t/t_var_bad_sameas.v:9: ... Location of original declaration
t/t_var_bad_sameas.v:9: ... Location of original declaration
%Error: t/t_var_bad_sameas.v:13: Unsupported in C: Variable has same name as cell: cellfirst
%Error: t/t_var_bad_sameas.v:14: Unsupported in C: Task has the same name as cell: cellfirst
%Error: t/t_var_bad_sameas.v:12: ... Location of original declaration
t/t_var_bad_sameas.v:12: ... Location of original declaration
%Error: t/t_var_bad_sameas.v:17: Unsupported in C: Variable has same name as task: taskfirst
%Error: t/t_var_bad_sameas.v:18: Unsupported in C: Cell has the same name as task: taskfirst
%Error: t/t_var_bad_sameas.v:16: ... Location of original declaration
t/t_var_bad_sameas.v:16: ... Location of original declaration
%Error: Exiting due to

2
test_regress/t/t_var_bad_sv.out
View File

@ -1,5 +1,5 @@
%Error: t/t_var_bad_sv.v:7: Unexpected "do": "do" is a SystemVerilog keyword misused as an identifier.
%Error: t/t_var_bad_sv.v:7: Modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.
... Modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.
%Error: t/t_var_bad_sv.v:8: Unexpected "do": "do" is a SystemVerilog keyword misused as an identifier.
%Error: t/t_var_bad_sv.v:8: syntax error, unexpected '(', expecting ')'
%Error: Exiting due to

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