mirror of
https://github.com/verilator/verilator.git
synced 2025-01-15 02:54:03 +00:00
12 lines
636 B
Plaintext
12 lines
636 B
Plaintext
|
%Warning-CLKDATA: t/t_clocker.v:45:17: Clock is assigned to part of data signal 'res8'
|
||
|
|
45 | assign res8 = {clk_3, 1'b0, clk_4};
|
||
|
|
| ^
|
||
|
|
... Use "/* verilator lint_off CLKDATA */" and lint_on around source to disable this message.
|
||
|
|
%Warning-CLKDATA: t/t_clocker.v:46:17: Clock is assigned to part of data signal 'res16'
|
||
|
|
46 | assign res16 = {count, clk_3, clk_1, clk_4};
|
||
|
|
| ^
|
||
|
|
%Warning-CLKDATA: t/t_clocker.v:57:14: Clock used as data (on rhs of assignment) in sequential block 'clk'
|
||
|
|
57 | res <= clk_final;
|
||
|
|
| ^~~~~~~~~
|
||
|
|
%Error: Exiting due to
|