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Fix internal pointer shown on CLKDATA warnings

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This commit is contained in:
Wilson Snyder 2020-11-25 21:34:56 -05:00
parent ac2058c7ec
commit 380137a402
5 changed files with 41 additions and 12 deletions
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4
src/V3Order.cpp
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@ -290,8 +290,8 @@ private:
// do the marking
if (m_hasClk) {
if (nodep->lhsp()->width() > m_rightClkWidth) {
nodep->v3warn(CLKDATA,
"Clock is assigned to part of data signal " << nodep->lhsp());
nodep->v3warn(CLKDATA, "Clock is assigned to part of data signal "
<< nodep->lhsp()->prettyNameQ());
UINFO(4, "CLKDATA: lhs with width " << nodep->lhsp()->width() << endl);
UINFO(4, " but rhs clock with width " << m_rightClkWidth << endl);
return; // skip the marking

2
test_regress/t/t_clocker.pl
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@ -11,7 +11,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
scenarios(simulator => 1);
compile(
verilator_flags2 => ["--trace"]
verilator_flags2 => ["--trace", "-Wno-CLKDATA"]
);
execute(

15
test_regress/t/t_clocker.v
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@ -18,6 +18,7 @@ module t (/*AUTOARG*/
);
input clk;
output reg res;
// When not inlining the below may trigger CLKDATA
output reg [7:0] res8;
output reg [15:0] res16;
@ -41,23 +42,19 @@ module t (/*AUTOARG*/
// the following two assignment triggers the CLKDATA warning
// because on LHS there are a mix of signals both CLOCK and
// DATA
/* verilator lint_off CLKDATA */
assign res8 = {clk_3, 1'b0, clk_4};
assign res16 = {count, clk_3, clk_1, clk_4};
/* verilator lint_on CLKDATA */
initial
count = 0;
count = 0;
always @(posedge clk_final or negedge clk_final) begin
count = count + 1;
// the following assignment should trigger the CLKDATA warning
// because CLOCK signal is used as DATA in sequential block
/* verilator lint_off CLKDATA */
res <= clk_final;
/* verilator lint_on CLKDATA */
count = count + 1;
// the following assignment should trigger the CLKDATA warning
// because CLOCK signal is used as DATA in sequential block
res <= clk_final;
if ( count == 8'hf) begin
$write("*-* All Finished *-*\n");
$finish;

11
test_regress/t/t_clocker_bad.out Normal file
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@ -0,0 +1,11 @@
%Warning-CLKDATA: t/t_clocker.v:45:17: Clock is assigned to part of data signal 'res8'
45 | assign res8 = {clk_3, 1'b0, clk_4};
| ^
... Use "/* verilator lint_off CLKDATA */" and lint_on around source to disable this message.
%Warning-CLKDATA: t/t_clocker.v:46:17: Clock is assigned to part of data signal 'res16'
46 | assign res16 = {count, clk_3, clk_1, clk_4};
| ^
%Warning-CLKDATA: t/t_clocker.v:57:14: Clock used as data (on rhs of assignment) in sequential block 'clk'
57 | res <= clk_final;
| ^~~~~~~~~
%Error: Exiting due to

21
test_regress/t/t_clocker_bad.pl Executable file
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@ -0,0 +1,21 @@
#!/usr/bin/env perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2004 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(vlt => 1);
top_filename("t/t_clocker.v");
lint(
fails => 1,
expect_filename => $Self->{golden_filename},
);
ok(1);
1;