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verilator/test_regress/t/t_verilated_debug.out

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Improve error messages on DIDNOTSETTLE, bug1556.
2019-11-07 00:47:34 +00:00
-V{t#,#}- Verilated::debug is on. Message prefix indicates {<thread>,<sequence_number>}.
Introduce model interface class, make $root part or Syms (#3036) This patch implements #3032. Verilator creates a module representing the SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was called the "TOP" module, which also acted as the user instantiated model class. Syms used to hold a pointer to this root module, but hold instances of any submodule. This patch renames this root scope module from "TOP" to "$root", and introduces a separate model class which is now an interface class. As the root module is no longer the user interface class, it can now be made an instance of Syms, just like any other submodule. This allows absolute references into the root module to avoid an additional pointer indirection resulting in a potential speedup (about 1.5% on OpenTitan). The model class now also contains all non design specific generated code (e.g.: eval loops, trace config, etc), which additionally simplifies Verilator internals. Please see the updated documentation for the model interface changes.
2021-06-21 14:30:20 +00:00
-V{t#,#}+ Vt_verilated_debug___024root___ctor_var_reset
Tests: Close some test coverage holes.
2019-07-01 01:53:01 +00:00
internalsDump:
Version: Verilator ###
Argv: obj_vlt/t_verilated_debug/Vt_verilated_debug
scopesDump:
Emit model implementation as loose methods. (#3006) This patch introduces the concept of 'loose' methods, which semantically are methods, but are declared as global functions, and are passed an explicit 'self' pointer. This enables these methods to be declared outside the class, only when they are needed, therefore removing the header dependency. The bulk of the emitted model implementation now uses loose methods.
2021-06-13 13:33:11 +00:00
-V{t#,#}+++++TOP Evaluate Vt_verilated_debug::eval_step
Introduce model interface class, make $root part or Syms (#3036) This patch implements #3032. Verilator creates a module representing the SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was called the "TOP" module, which also acted as the user instantiated model class. Syms used to hold a pointer to this root module, but hold instances of any submodule. This patch renames this root scope module from "TOP" to "$root", and introduces a separate model class which is now an interface class. As the root module is no longer the user interface class, it can now be made an instance of Syms, just like any other submodule. This allows absolute references into the root module to avoid an additional pointer indirection resulting in a potential speedup (about 1.5% on OpenTitan). The model class now also contains all non design specific generated code (e.g.: eval loops, trace config, etc), which additionally simplifies Verilator internals. Please see the updated documentation for the model interface changes.
2021-06-21 14:30:20 +00:00
-V{t#,#}+ Vt_verilated_debug___024root___eval_debug_assertions
-V{t#,#}+ Vt_verilated_debug___024root___eval_initial
-V{t#,#}+ Vt_verilated_debug___024root___initial__TOP__1
Tests: Cover some internal code coverage issues
2021-03-07 18:52:37 +00:00
Data: w96: 000000aa 000000bb 000000cc
Emit model implementation as loose methods. (#3006) This patch introduces the concept of 'loose' methods, which semantically are methods, but are declared as global functions, and are passed an explicit 'self' pointer. This enables these methods to be declared outside the class, only when they are needed, therefore removing the header dependency. The bulk of the emitted model implementation now uses loose methods.
2021-06-13 13:33:11 +00:00
-V{t#,#}+ Initial loop
Introduce model interface class, make $root part or Syms (#3036) This patch implements #3032. Verilator creates a module representing the SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was called the "TOP" module, which also acted as the user instantiated model class. Syms used to hold a pointer to this root module, but hold instances of any submodule. This patch renames this root scope module from "TOP" to "$root", and introduces a separate model class which is now an interface class. As the root module is no longer the user interface class, it can now be made an instance of Syms, just like any other submodule. This allows absolute references into the root module to avoid an additional pointer indirection resulting in a potential speedup (about 1.5% on OpenTitan). The model class now also contains all non design specific generated code (e.g.: eval loops, trace config, etc), which additionally simplifies Verilator internals. Please see the updated documentation for the model interface changes.
2021-06-21 14:30:20 +00:00
-V{t#,#}+ Vt_verilated_debug___024root___eval_settle
-V{t#,#}+ Vt_verilated_debug___024root___eval
Improve error messages on DIDNOTSETTLE, bug1556.
2019-11-07 00:47:34 +00:00
-V{t#,#}+ Clock loop
Introduce model interface class, make $root part or Syms (#3036) This patch implements #3032. Verilator creates a module representing the SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was called the "TOP" module, which also acted as the user instantiated model class. Syms used to hold a pointer to this root module, but hold instances of any submodule. This patch renames this root scope module from "TOP" to "$root", and introduces a separate model class which is now an interface class. As the root module is no longer the user interface class, it can now be made an instance of Syms, just like any other submodule. This allows absolute references into the root module to avoid an additional pointer indirection resulting in a potential speedup (about 1.5% on OpenTitan). The model class now also contains all non design specific generated code (e.g.: eval loops, trace config, etc), which additionally simplifies Verilator internals. Please see the updated documentation for the model interface changes.
2021-06-21 14:30:20 +00:00
-V{t#,#}+ Vt_verilated_debug___024root___eval
Emit model implementation as loose methods. (#3006) This patch introduces the concept of 'loose' methods, which semantically are methods, but are declared as global functions, and are passed an explicit 'self' pointer. This enables these methods to be declared outside the class, only when they are needed, therefore removing the header dependency. The bulk of the emitted model implementation now uses loose methods.
2021-06-13 13:33:11 +00:00
-V{t#,#}+++++TOP Evaluate Vt_verilated_debug::eval_step
Introduce model interface class, make $root part or Syms (#3036) This patch implements #3032. Verilator creates a module representing the SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was called the "TOP" module, which also acted as the user instantiated model class. Syms used to hold a pointer to this root module, but hold instances of any submodule. This patch renames this root scope module from "TOP" to "$root", and introduces a separate model class which is now an interface class. As the root module is no longer the user interface class, it can now be made an instance of Syms, just like any other submodule. This allows absolute references into the root module to avoid an additional pointer indirection resulting in a potential speedup (about 1.5% on OpenTitan). The model class now also contains all non design specific generated code (e.g.: eval loops, trace config, etc), which additionally simplifies Verilator internals. Please see the updated documentation for the model interface changes.
2021-06-21 14:30:20 +00:00
-V{t#,#}+ Vt_verilated_debug___024root___eval_debug_assertions
Improve error messages on DIDNOTSETTLE, bug1556.
2019-11-07 00:47:34 +00:00
-V{t#,#}+ Clock loop
Introduce model interface class, make $root part or Syms (#3036) This patch implements #3032. Verilator creates a module representing the SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was called the "TOP" module, which also acted as the user instantiated model class. Syms used to hold a pointer to this root module, but hold instances of any submodule. This patch renames this root scope module from "TOP" to "$root", and introduces a separate model class which is now an interface class. As the root module is no longer the user interface class, it can now be made an instance of Syms, just like any other submodule. This allows absolute references into the root module to avoid an additional pointer indirection resulting in a potential speedup (about 1.5% on OpenTitan). The model class now also contains all non design specific generated code (e.g.: eval loops, trace config, etc), which additionally simplifies Verilator internals. Please see the updated documentation for the model interface changes.
2021-06-21 14:30:20 +00:00
-V{t#,#}+ Vt_verilated_debug___024root___eval
-V{t#,#}+ Vt_verilated_debug___024root___sequent__TOP__2
Unify format of VL_DEBUG print messages
2017-10-25 02:56:58 +00:00
*-* All Finished *-*
Introduce model interface class, make $root part or Syms (#3036) This patch implements #3032. Verilator creates a module representing the SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was called the "TOP" module, which also acted as the user instantiated model class. Syms used to hold a pointer to this root module, but hold instances of any submodule. This patch renames this root scope module from "TOP" to "$root", and introduces a separate model class which is now an interface class. As the root module is no longer the user interface class, it can now be made an instance of Syms, just like any other submodule. This allows absolute references into the root module to avoid an additional pointer indirection resulting in a potential speedup (about 1.5% on OpenTitan). The model class now also contains all non design specific generated code (e.g.: eval loops, trace config, etc), which additionally simplifies Verilator internals. Please see the updated documentation for the model interface changes.
2021-06-21 14:30:20 +00:00
-V{t#,#}+ Vt_verilated_debug___024root___final
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