mirror of
https://github.com/verilator/verilator.git
synced 2025-01-01 04:07:34 +00:00
Unify format of VL_DEBUG print messages
This commit is contained in:
parent
e403db5877
commit
5ead61dc7b
@ -96,6 +96,37 @@ void VL_FATAL_MT (const char* filename, int linenum, const char* hier, const cha
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vl_fatal(filename, linenum, hier, msg);
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}
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//===========================================================================
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// Debug prints
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/// sprintf but return as string (this isn't fast, for print messages only)
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std::string _vl_string_vprintf(const char* formatp, va_list ap) {
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int len = VL_VSNPRINTF(NULL, 0, formatp, ap);
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if (VL_UNLIKELY(len < 1)) return "";
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char* bufp = new char[len+1];
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VL_VSNPRINTF(bufp, len+1, formatp, ap);
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std::string out = std::string(bufp, len);
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delete bufp;
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return out;
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}
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vluint64_t _vl_dbg_sequence_number() {
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static vluint64_t sequence = 0;
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return ++sequence;
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}
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vluint32_t _vl_dbg_thread_number() {
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return 0;
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}
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void VL_DBG_MSGF(const char* formatp, ...) {
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va_list ap;
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va_start(ap, formatp);
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std::string out = _vl_string_vprintf(formatp, ap);
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va_end(ap);
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VL_PRINTF_MT("-V{t%d,%" VL_PRI64 "d}%s", _vl_dbg_thread_number(), _vl_dbg_sequence_number(), out.c_str());
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}
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//===========================================================================
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// Overall class init
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@ -631,7 +662,7 @@ static inline void _vl_vsss_read(FILE* fp, int& floc, WDataInP fromp, const std:
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_vl_vsss_advance(fp, floc);
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}
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*cp++ = '\0';
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//VL_PRINTF_MT("\t_read got='%s'\n", tmpp);
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//VL_DBG_MSG("\t_read got='"<<tmpp<<"'\n");
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}
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static inline void _vl_vsss_setbit(WDataOutP owp, int obits, int lsb, int nbits, IData ld) {
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for (; nbits && lsb<obits; nbits--, lsb++, ld>>=1) {
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@ -678,7 +709,7 @@ IData _vl_vsscanf(FILE* fp, // If a fscanf
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bool inPct = false;
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const char* pos = formatp;
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for (; *pos && !_vl_vsss_eof(fp,floc); ++pos) {
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//VL_PRINTF_MT("_vlscan fmt='%c' floc=%d file='%c'\n", pos[0], floc, _vl_vsss_peek(fp,floc,fromp,fstr));
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//VL_DBG_MSG("_vlscan fmt='"<<pos[0]<<"' floc="<<floc<<" file='"<<_vl_vsss_peek(fp,floc,fromp,fstr)<<"'"<<endl);
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if (!inPct && pos[0]=='%') {
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inPct = true;
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} else if (!inPct && isspace(pos[0])) { // Format spaces
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@ -1295,6 +1326,17 @@ std::string VL_CVT_PACK_STR_NW(int lwords, WDataInP lwp) {
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//===========================================================================
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// Verilated:: Methods
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void Verilated::debug(int val) {
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s_s.s_debug = val;
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if (val) {
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#ifdef VL_DEBUG
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VL_DEBUG_IF(VL_DBG_MSGF("- Verilated::debug is on. Message prefix indicates {<thread>,<sequence_number>}.\n"););
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#else
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VL_PRINTF_MT("- Verilated::debug attempted, but compiled without VL_DEBUG, so messages suppressed.\n");
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#endif
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}
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}
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const char* Verilated::catName(const char* n1, const char* n2) {
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// Returns new'ed data
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// Used by symbol table creation to make module names
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@ -248,7 +248,7 @@ public:
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static int randReset() { return s_s.s_randReset; } ///< Return randReset value
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/// Enable debug of internal verilated code
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static inline void debug(int level) { s_s.s_debug = level; }
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static void debug(int level);
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#ifdef VL_DEBUG
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static inline int debug() { return s_s.s_debug; } ///< Return debug value
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#else
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@ -354,6 +354,8 @@ extern void VL_FATAL_MT (const char* filename, int linenum, const char* hier,
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const char* msg);
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/// Print a string, multithread safe. Eventually VL_PRINTF will get called.
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#define VL_PRINTF_MT VL_PRINTF
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/// Print a debug message from internals with standard prefix, with printf style format
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extern void VL_DBG_MSGF(const char* formatp, ...);
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extern IData VL_RANDOM_I(int obits); ///< Randomize a signal
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extern QData VL_RANDOM_Q(int obits); ///< Randomize a signal
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@ -112,7 +112,7 @@ void VerilatedDeserialize::trailer() {
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void VerilatedSave::open (const char* filenamep) {
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if (isOpen()) return;
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VL_DEBUG_IF(VL_PRINTF_MT("-vltSave: opening save file %s\n",filenamep););
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VL_DEBUG_IF(VL_DBG_MSGF("- save: opening save file %s\n",filenamep););
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if (filenamep[0]=='|') {
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assert(0); // Not supported yet.
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@ -134,7 +134,7 @@ void VerilatedSave::open (const char* filenamep) {
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void VerilatedRestore::open (const char* filenamep) {
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if (isOpen()) return;
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VL_DEBUG_IF(VL_PRINTF_MT("-vltRestore: opening restore file %s\n",filenamep););
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VL_DEBUG_IF(VL_DBG_MSGF("- restore: opening restore file %s\n",filenamep););
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if (filenamep[0]=='|') {
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assert(0); // Not supported yet.
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@ -317,7 +317,7 @@ void VerilatedVcd::printTime (vluint64_t timeui) {
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static VL_THREAD_LOCAL bool backTime = false;
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if (!backTime) {
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backTime = true;
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VL_PRINTF_MT("VCD time is moving backwards, wave file may be incorrect.\n");
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VL_PRINTF_MT("%%Warning: VCD time is moving backwards, wave file may be incorrect.\n");
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}
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}
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m_timeLastDump = timeui;
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@ -361,7 +361,7 @@ public:
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if (VL_UNLIKELY(it->first <= time)) {
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VerilatedVpioCb* vop = it->second;
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++it; // iterator may be deleted by callback
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VL_DEBUG_IF_PLI(VL_PRINTF_MT("-vltVpi: timed_callback %p\n",vop););
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VL_DEBUG_IF_PLI(VL_DBG_MSGF("- vpi: timed_callback %p\n",vop););
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(vop->cb_rtnp()) (vop->cb_datap());
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}
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else { ++it; }
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@ -383,7 +383,7 @@ public:
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continue;
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}
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VerilatedVpioCb* vop = *it++;
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VL_DEBUG_IF_PLI(VL_PRINTF_MT("-vltVpi: reason_callback %d %p\n",reason,vop););
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VL_DEBUG_IF_PLI(VL_DBG_MSGF("- vpi: reason_callback %d %p\n",reason,vop););
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(vop->cb_rtnp()) (vop->cb_datap());
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}
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}
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@ -400,11 +400,11 @@ public:
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if (VerilatedVpioVar* varop = VerilatedVpioVar::castp(vop->cb_datap()->obj)) {
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void* newDatap = varop->varDatap();
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void* prevDatap = varop->prevDatap(); // Was malloced when we added the callback
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VL_DEBUG_IF_PLI(VL_PRINTF_MT("-vltVpi: value_test %s v[0]=%d/%d %p %p\n",
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VL_DEBUG_IF_PLI(VL_DBG_MSGF("- vpi: value_test %s v[0]=%d/%d %p %p\n",
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varop->fullname(), *((CData*)newDatap), *((CData*)prevDatap),
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newDatap, prevDatap););
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if (memcmp(prevDatap, newDatap, varop->entSize())) {
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VL_DEBUG_IF_PLI(VL_PRINTF_MT("-vltVpi: value_callback %p %s v[0]=%d\n",
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VL_DEBUG_IF_PLI(VL_DBG_MSGF("- vpi: value_callback %p %s v[0]=%d\n",
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vop,varop->fullname(), *((CData*)newDatap)););
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update.insert(varop);
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vpi_get_value(vop->cb_datap()->obj, vop->cb_datap()->value);
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@ -913,7 +913,7 @@ vpiHandle vpi_register_cb(p_cb_data cb_data_p) {
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QData time = 0;
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if (cb_data_p->time) time = _VL_SET_QII(cb_data_p->time->high, cb_data_p->time->low);
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VerilatedVpioCb* vop = new VerilatedVpioCb(cb_data_p, VL_TIME_Q()+time);
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VL_DEBUG_IF_PLI(VL_PRINTF_MT("-vltVpi: vpi_register_cb %d %p delay=%" VL_PRI64 "u\n",cb_data_p->reason,vop,time););
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VL_DEBUG_IF_PLI(VL_DBG_MSGF("- vpi: vpi_register_cb %d %p delay=%" VL_PRI64 "u\n",cb_data_p->reason,vop,time););
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VerilatedVpiImp::cbTimedAdd(vop);
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return vop->castVpiHandle();
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}
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@ -928,7 +928,7 @@ vpiHandle vpi_register_cb(p_cb_data cb_data_p) {
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case cbExitInteractive: // FALLTHRU // NOP, but need to return handle, so make object
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case cbInteractiveScopeChange: { // FALLTHRU // NOP, but need to return handle, so make object
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VerilatedVpioCb* vop = new VerilatedVpioCb(cb_data_p, 0);
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VL_DEBUG_IF_PLI(VL_PRINTF_MT("-vltVpi: vpi_register_cb %d %p\n",cb_data_p->reason,vop););
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VL_DEBUG_IF_PLI(VL_DBG_MSGF("- vpi: vpi_register_cb %d %p\n",cb_data_p->reason,vop););
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VerilatedVpiImp::cbReasonAdd(vop);
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return vop->castVpiHandle();
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}
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@ -940,7 +940,7 @@ vpiHandle vpi_register_cb(p_cb_data cb_data_p) {
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}
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PLI_INT32 vpi_remove_cb(vpiHandle object) {
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VL_DEBUG_IF_PLI(VL_PRINTF_MT("-vltVpi: vpi_remove_cb %p\n",object););
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VL_DEBUG_IF_PLI(VL_DBG_MSGF("- vpi: vpi_remove_cb %p\n",object););
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VerilatedVpioCb* vop = VerilatedVpioCb::castp(object);
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_VL_VPI_ERROR_RESET(); // reset vpi error status
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if (VL_UNLIKELY(!vop)) return 0;
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@ -967,7 +967,7 @@ void vpi_get_systf_info(vpiHandle object, p_vpi_systf_data systf_data_p) {
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vpiHandle vpi_handle_by_name(PLI_BYTE8* namep, vpiHandle scope) {
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_VL_VPI_ERROR_RESET(); // reset vpi error status
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if (VL_UNLIKELY(!namep)) return NULL;
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VL_DEBUG_IF_PLI(VL_PRINTF_MT("-vltVpi: vpi_handle_by_name %s %p\n",namep,scope););
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VL_DEBUG_IF_PLI(VL_DBG_MSGF("- vpi: vpi_handle_by_name %s %p\n",namep,scope););
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VerilatedVpioScope* voScopep = VerilatedVpioScope::castp(scope);
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const VerilatedVar* varp;
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const VerilatedScope* scopep;
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@ -999,7 +999,7 @@ vpiHandle vpi_handle_by_name(PLI_BYTE8* namep, vpiHandle scope) {
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vpiHandle vpi_handle_by_index(vpiHandle object, PLI_INT32 indx) {
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// Used to get array entries
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VL_DEBUG_IF_PLI(VL_PRINTF_MT("-vltVpi: vpi_handle_by_index %p %d\n",object, indx););
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VL_DEBUG_IF_PLI(VL_DBG_MSGF("- vpi: vpi_handle_by_index %p %d\n",object, indx););
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VerilatedVpioVar* varop = VerilatedVpioVar::castp(object);
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_VL_VPI_ERROR_RESET(); // reset vpi error status
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if (VL_LIKELY(varop)) {
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@ -1024,7 +1024,7 @@ vpiHandle vpi_handle_by_index(vpiHandle object, PLI_INT32 indx) {
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// for traversing relationships
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vpiHandle vpi_handle(PLI_INT32 type, vpiHandle object) {
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VL_DEBUG_IF_PLI(VL_PRINTF_MT("-vltVpi: vpi_handle %d %p\n",type,object););
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VL_DEBUG_IF_PLI(VL_DBG_MSGF("- vpi: vpi_handle %d %p\n",type,object););
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_VL_VPI_ERROR_RESET(); // reset vpi error status
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switch (type) {
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case vpiLeftRange: {
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@ -1066,7 +1066,7 @@ vpiHandle vpi_handle_multi(PLI_INT32 type, vpiHandle refHandle1, vpiHandle refHa
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}
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vpiHandle vpi_iterate(PLI_INT32 type, vpiHandle object) {
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VL_DEBUG_IF_PLI(VL_PRINTF_MT("-vltVpi: vpi_iterate %d %p\n",type,object););
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VL_DEBUG_IF_PLI(VL_DBG_MSGF("- vpi: vpi_iterate %d %p\n",type,object););
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_VL_VPI_ERROR_RESET(); // reset vpi error status
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switch (type) {
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case vpiMemoryWord: {
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@ -1103,7 +1103,7 @@ vpiHandle vpi_iterate(PLI_INT32 type, vpiHandle object) {
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}
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}
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vpiHandle vpi_scan(vpiHandle object) {
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VL_DEBUG_IF_PLI(VL_PRINTF_MT("-vltVpi: vpi_scan %p\n",object););
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VL_DEBUG_IF_PLI(VL_DBG_MSGF("- vpi: vpi_scan %p\n",object););
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_VL_VPI_ERROR_RESET(); // reset vpi error status
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VerilatedVpio* vop = VerilatedVpio::castp(object);
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if (VL_UNLIKELY(!vop)) return NULL;
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@ -1114,7 +1114,7 @@ vpiHandle vpi_scan(vpiHandle object) {
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PLI_INT32 vpi_get(PLI_INT32 property, vpiHandle object) {
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// Leave this in the header file - in many cases the compiler can constant propagate "object"
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VL_DEBUG_IF_PLI(VL_PRINTF_MT("-vltVpi: vpi_get %d %p\n",property,object););
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VL_DEBUG_IF_PLI(VL_DBG_MSGF("- vpi: vpi_get %d %p\n",property,object););
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_VL_VPI_ERROR_RESET(); // reset vpi error status
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switch (property) {
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case vpiTimePrecision: {
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@ -1155,7 +1155,7 @@ PLI_INT64 vpi_get64(PLI_INT32 property, vpiHandle object) {
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}
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PLI_BYTE8 *vpi_get_str(PLI_INT32 property, vpiHandle object) {
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VL_DEBUG_IF_PLI(VL_PRINTF_MT("-vltVpi: vpi_get_str %d %p\n",property,object););
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VL_DEBUG_IF_PLI(VL_DBG_MSGF("- vpi: vpi_get_str %d %p\n",property,object););
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VerilatedVpio* vop = VerilatedVpio::castp(object);
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_VL_VPI_ERROR_RESET(); // reset vpi error status
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if (VL_UNLIKELY(!vop)) return NULL;
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@ -1193,7 +1193,7 @@ void vpi_get_value(vpiHandle object, p_vpi_value value_p) {
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static VL_THREAD_LOCAL char outStr[1+VL_MULS_MAX_WORDS*32]; // Maximum required size is for binary string, one byte per bit plus null termination
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// cppcheck-suppress variableScope
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static VL_THREAD_LOCAL int outStrSz = sizeof(outStr)-1;
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VL_DEBUG_IF_PLI(VL_PRINTF_MT("-vltVpi: vpi_get_value %p\n",object););
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VL_DEBUG_IF_PLI(VL_DBG_MSGF("- vpi: vpi_get_value %p\n",object););
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_VL_VPI_ERROR_RESET(); // reset vpi error status
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if (VL_UNLIKELY(!value_p)) return;
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if (VerilatedVpioVar* vop = VerilatedVpioVar::castp(object)) {
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@ -1448,16 +1448,16 @@ void vpi_get_value(vpiHandle object, p_vpi_value value_p) {
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vpiHandle vpi_put_value(vpiHandle object, p_vpi_value value_p,
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p_vpi_time time_p, PLI_INT32 flags) {
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VL_DEBUG_IF_PLI(VL_PRINTF_MT("-vltVpi: vpi_put_value %p %p\n",object, value_p););
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VL_DEBUG_IF_PLI(VL_DBG_MSGF("- vpi: vpi_put_value %p %p\n",object, value_p););
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_VL_VPI_ERROR_RESET(); // reset vpi error status
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if (VL_UNLIKELY(!value_p)) {
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_VL_VPI_WARNING(__FILE__, __LINE__, "Ignoring vpi_put_value with NULL value pointer");
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return 0;
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}
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if (VerilatedVpioVar* vop = VerilatedVpioVar::castp(object)) {
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VL_DEBUG_IF_PLI(VL_PRINTF_MT("-vltVpi: vpi_put_value name=%s fmt=%d vali=%d\n",
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VL_DEBUG_IF_PLI(VL_DBG_MSGF("- vpi: vpi_put_value name=%s fmt=%d vali=%d\n",
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vop->fullname(), value_p->format, value_p->value.integer);
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VL_PRINTF_MT("-vltVpi: varp=%p putatp=%p\n",
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VL_DBG_MSGF("- vpi: varp=%p putatp=%p\n",
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vop->varp()->datap(), vop->varDatap()););
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if (VL_UNLIKELY(!vop->varp()->isPublicRW())) {
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_VL_VPI_WARNING(__FILE__, __LINE__, "Ignoring vpi_put_value to signal marked read-only, use public_flat_rw instead: ", vop->fullname());
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@ -1822,7 +1822,7 @@ PLI_INT32 vpi_free_object(vpiHandle object) {
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}
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PLI_INT32 vpi_release_handle (vpiHandle object) {
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VL_DEBUG_IF_PLI(VL_PRINTF_MT("-vltVpi: vpi_release_handle %p\n",object););
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VL_DEBUG_IF_PLI(VL_DBG_MSGF("- vpi: vpi_release_handle %p\n",object););
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VerilatedVpio* vop = VerilatedVpio::castp(object);
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_VL_VPI_ERROR_RESET(); // reset vpi error status
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if (VL_UNLIKELY(!vop)) return 0;
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@ -1856,7 +1856,7 @@ PLI_INT32 vpi_put_userdata(vpiHandle obj, void *userdata) {
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}
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PLI_INT32 vpi_control(PLI_INT32 operation, ...) {
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VL_DEBUG_IF_PLI(VL_PRINTF_MT("-vltVpi: vpi_control %d\n",operation););
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VL_DEBUG_IF_PLI(VL_DBG_MSGF("- vpi: vpi_control %d\n",operation););
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_VL_VPI_ERROR_RESET(); // reset vpi error status
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switch (operation) {
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case vpiFinish: {
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@ -877,7 +877,8 @@ class EmitCImp : EmitCStmts {
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puts(modClassName(m_modp)+"::"+nodep->name()
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+"("+cFuncArgs(nodep)+") {\n");
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puts("VL_DEBUG_IF(VL_PRINTF_MT(\" ");
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// "+" in the debug indicates a print from the model
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puts("VL_DEBUG_IF(VL_DBG_MSGF(\"+ ");
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for (int i=0;i<m_modp->level();i++) { puts(" "); }
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puts(modClassName(m_modp)+"::"+nodep->name()
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+"\\n\"); );\n");
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@ -938,7 +939,7 @@ class EmitCImp : EmitCStmts {
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if (nodep->lhsp()->castVarRef()) {
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varname = ": "+nodep->lhsp()->castVarRef()->varp()->prettyName();
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}
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puts(")) VL_PRINTF_MT(\"\tCHANGE: "+nodep->fileline()->ascii()
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puts(")) VL_DBG_MSGF(\" CHANGE: "+nodep->fileline()->ascii()
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+varname+"\\n\"); );\n");
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}
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}
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@ -1738,11 +1739,11 @@ void EmitCImp::emitWrapEval(AstNodeModule* modp) {
|
||||
puts("if (VL_UNLIKELY(__Vm_inhibitSim)) return;\n");
|
||||
}
|
||||
putsDecoration("// Evaluate till stable\n");
|
||||
puts("VL_DEBUG_IF(VL_PRINTF_MT(\"\\n----TOP Evaluate "+modClassName(modp)+"::eval\\n\"); );\n");
|
||||
puts("VL_DEBUG_IF(VL_DBG_MSGF(\"+++++TOP Evaluate "+modClassName(modp)+"::eval\\n\"); );\n");
|
||||
puts("int __VclockLoop = 0;\n");
|
||||
puts("QData __Vchange = 1;\n");
|
||||
puts("while (VL_LIKELY(__Vchange)) {\n");
|
||||
puts( "VL_DEBUG_IF(VL_PRINTF_MT(\" Clock loop\\n\"););\n");
|
||||
puts( "VL_DEBUG_IF(VL_DBG_MSGF(\"+ Clock loop\\n\"););\n");
|
||||
if (v3Global.opt.trace()) {
|
||||
puts("vlSymsp->__Vm_activity = true;\n");
|
||||
}
|
||||
|
18
test_regress/t/t_verilated_debug.out
Normal file
18
test_regress/t/t_verilated_debug.out
Normal file
@ -0,0 +1,18 @@
|
||||
-V{t0,1}- Verilated::debug is on. Message prefix indicates {<thread>,<sequence_number>}.
|
||||
-V{t0,2}+ Vt_verilated_debug::_ctor_var_reset
|
||||
-V{t0,3}+ Vt_verilated_debug::_eval_initial
|
||||
-V{t0,4}+ Vt_verilated_debug::_eval_settle
|
||||
-V{t0,5}+ Vt_verilated_debug::_eval
|
||||
-V{t0,6}+ Vt_verilated_debug::_change_request
|
||||
-V{t0,7}+++++TOP Evaluate Vt_verilated_debug::eval
|
||||
-V{t0,8}+ Clock loop
|
||||
-V{t0,9}+ Vt_verilated_debug::_eval
|
||||
-V{t0,10}+ Vt_verilated_debug::_change_request
|
||||
-V{t0,11}+++++TOP Evaluate Vt_verilated_debug::eval
|
||||
-V{t0,12}+ Clock loop
|
||||
-V{t0,13}+ Vt_verilated_debug::_eval
|
||||
-V{t0,14}+ Vt_verilated_debug::_sequent__TOP__1
|
||||
*-* All Finished *-*
|
||||
- t/t_verilated_debug.v:16: Verilog $finish
|
||||
-V{t0,15}+ Vt_verilated_debug::_change_request
|
||||
-V{t0,16}+ Vt_verilated_debug::final
|
23
test_regress/t/t_verilated_debug.pl
Executable file
23
test_regress/t/t_verilated_debug.pl
Executable file
@ -0,0 +1,23 @@
|
||||
#!/usr/bin/perl
|
||||
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
|
||||
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
|
||||
#
|
||||
# Copyright 2003 by Wilson Snyder. This program is free software; you can
|
||||
# redistribute it and/or modify it under the terms of either the GNU
|
||||
# Lesser General Public License Version 3 or the Perl Artistic License
|
||||
# Version 2.0.
|
||||
|
||||
$Self->{verilated_debug} = 1;
|
||||
|
||||
compile (
|
||||
verilator_flags2 => [],
|
||||
);
|
||||
|
||||
execute (
|
||||
check_finished=>1,
|
||||
);
|
||||
|
||||
ok(files_identical("$Self->{obj_dir}/vlt_sim.log", "t/$Self->{name}.out"));
|
||||
|
||||
ok(1);
|
||||
1;
|
19
test_regress/t/t_verilated_debug.v
Normal file
19
test_regress/t/t_verilated_debug.v
Normal file
@ -0,0 +1,19 @@
|
||||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed into the Public Domain, for any use,
|
||||
// without warranty, 2017 by Wilson Snyder.
|
||||
|
||||
module t (/*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
|
||||
input clk;
|
||||
|
||||
// Test loop
|
||||
always @ (posedge clk) begin
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
|
||||
endmodule
|
Loading…
Reference in New Issue
Block a user