verilator/test_regress/t/t_assert_synth_parallel_vlt.out

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[40] %Error: t_assert_synth.v:55: Assertion failed in top.t: synthesis parallel_case, but multiple matches found
%Error: t/t_assert_synth.v:55: Verilog $stop
Aborting...
Add SPDX license identifiers. No functional change. 2020-03-21 15:24:24 +00:00			`[40] %Error: t_assert_synth.v:55: Assertion failed in top.t: synthesis parallel_case, but multiple matches found`
			`%Error: t/t_assert_synth.v:55: Verilog $stop`
Tests: Favor use of expect_filename. No functional change. 2020-03-14 21:42:15 +00:00			`Aborting...`