2017-11-22 02:10:42 +00:00
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// DESCRIPTION: Verilator: Verilog Test module
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//
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2020-03-21 15:24:24 +00:00
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2007 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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2017-11-22 02:10:42 +00:00
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module t (/*AUTOARG*/);
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if (1) begin
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2020-09-19 14:30:31 +00:00
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$info;
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2021-03-18 22:46:07 +00:00
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$info("User elaboration-time info");
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2020-09-19 14:30:31 +00:00
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$warning;
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2021-03-18 22:46:07 +00:00
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$warning("User elaboration-time warning");
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2019-08-05 01:50:08 +00:00
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$warning(1); // Check can convert arguments to format
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2020-09-19 14:30:31 +00:00
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$error;
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2021-03-18 22:46:07 +00:00
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$error("User elaboration-time error");
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$fatal(0, "User elaboration-time fatal");
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2017-11-22 02:10:42 +00:00
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end
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endmodule
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