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Internal coverage improvements

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This commit is contained in:
Wilson Snyder 2020-09-19 10:30:31 -04:00
parent 87e4a86fbb
commit 1a127a479c
19 changed files with 180 additions and 16 deletions
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32
test_regress/t/t_assert_comp_bad.out
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@ -1,18 +1,34 @@
-Info: t/t_assert_comp_bad.v:10:7: User compile-time info
-Info: t/t_assert_comp_bad.v:10:7:
: ... In instance t
10 | $info("User compile-time info");
10 | $info;
| ^~~~~
%Warning-USERWARN: t/t_assert_comp_bad.v:11:7: User compile-time warning
-Info: t/t_assert_comp_bad.v:11:7: User compile-time info
: ... In instance t
11 | $info("User compile-time info");
| ^~~~~
%Warning-USERWARN: t/t_assert_comp_bad.v:12:7:
: ... In instance t
11 | $warning("User compile-time warning");
12 | $warning;
| ^~~~~~~~
... Use "/* verilator lint_off USERWARN */" and lint_on around source to disable this message.
%Warning-USERWARN: t/t_assert_comp_bad.v:12:7: 1
%Warning-USERWARN: t/t_assert_comp_bad.v:13:7: User compile-time warning
: ... In instance t
12 | $warning(1);
13 | $warning("User compile-time warning");
| ^~~~~~~~
%Warning-USERERROR: t/t_assert_comp_bad.v:13:7: User compile-time error
%Warning-USERWARN: t/t_assert_comp_bad.v:14:7: 1
: ... In instance t
14 | $warning(1);
| ^~~~~~~~
%Warning-USERERROR: t/t_assert_comp_bad.v:15:7:
: ... In instance t
13 | $error("User compile-time error");
15 | $error;
| ^~~~~~
%Warning-USERERROR: t/t_assert_comp_bad.v:16:7: User compile-time error
: ... In instance t
16 | $error("User compile-time error");
| ^~~~~~
%Warning-USERFATAL: t/t_assert_comp_bad.v:17:7:
: ... In instance t
17 | $fatal;
| ^~~~~~
%Error: Exiting due to

4
test_regress/t/t_assert_comp_bad.v
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@ -7,10 +7,14 @@
module t (/*AUTOARG*/);
if (1) begin
$info;
$info("User compile-time info");
$warning;
$warning("User compile-time warning");
$warning(1); // Check can convert arguments to format
$error;
$error("User compile-time error");
$fatal;
end
endmodule

2
test_regress/t/t_class_new.v
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@ -8,7 +8,7 @@ class ClsNoArg;
const int imembera; // Ok for new() to assign to a const
function new();
imembera = 5;
endfunction
endfunction : new
endclass
class ClsArg;

22
test_regress/t/t_debug_emitv_addrids.pl Executable file
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@ -0,0 +1,22 @@
#!/usr/bin/env perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(vlt => 1);
top_filename("t/t_debug_emitv.v");
lint(
# We also have dump-tree turned on, so hit a lot of AstNode*::dump() functions
# Likewise XML
v_flags => ["--lint-only --dump-treei 9 --dump-tree-addrids"],
);
ok(1);
1;

4
test_regress/t/t_display.out
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@ -44,9 +44,13 @@
[0] %6s=: !: %6s=: what!: %6s=: hmmm!1234:
[0] %8s=: sv-str:
d: 12 12
h: 00c 00c
o: 014 014
b: 000001100 000001100
[0] hello, from a very long string. Percent %s are literally substituted in.
hello, from a concatenated string.
hello, from a concatenated format string [0].

4
test_regress/t/t_display.v
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@ -135,9 +135,13 @@ module t;
// Displays without format, must use default
$write("d: "); $write(nine); $write(" "); $display(nine);
$write; $display;
$writeh("h: "); $writeh(nine); $writeh(" "); $displayh(nine);
$writeh; $displayh;
$writeo("o: "); $writeo(nine); $writeo(" "); $displayo(nine);
$writeb; $displayb;
$writeb("b: "); $writeb(nine); $writeb(" "); $displayb(nine);
$writeo; $displayo;
$display("[%0t] %s%s%s", $time,
"hel", "lo, fr", "om a very long string. Percent %s are literally substituted in.");

7
test_regress/t/t_preproc_defarg_bad.out Normal file
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@ -0,0 +1,7 @@
%Error: t/t_preproc_defarg_bad.v:13:4: Illegal text before '(' that starts define arguments
%Error: t/t_preproc_defarg_bad.v:13:8: Define passed too many arguments: A1
%Error: t/t_preproc_defarg_bad.v:15:4: Illegal text before '(' that starts define arguments
%Error: t/t_preproc_defarg_bad.v:16:10: Define passed too many arguments: A2
%Error: t/t_preproc_defarg_bad.v:21:1: EOF in define argument list
%Error: t/t_preproc_defarg_bad.v:21:1: Expecting ( to begin argument list for define reference `A2
%Error: Exiting due to

21
test_regress/t/t_preproc_defarg_bad.pl Executable file
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@ -0,0 +1,21 @@
#!/usr/bin/env perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(vlt => 1);
lint(
fails => 1,
verilator_flags2 => ["-Wno-context"],
# The .vh file has the error, not the .v file
expect_filename => $Self->{golden_filename},
);
ok(1);
1;

19
test_regress/t/t_preproc_defarg_bad.v Normal file
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@ -0,0 +1,19 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2010 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
//See bug289
`define A1(x)
`define A2(x,y)
`A1
`A1(1,2)
`A2
`A2(1)
`A2(1,2,3)
module t;
endmodule

16
test_regress/t/t_preproc_elsif_bad.out Normal file
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@ -0,0 +1,16 @@
%Error: t/t_preproc_elsif_bad.v:9:8: `elsif with no matching `if
9 | `elsif A
| ^
%Error: t/t_preproc_elsif_bad.v:10:1: `endif with no matching `if
10 | `endif
| ^~~~~~
%Error: t/t_preproc_elsif_bad.v:12:1: `else with no matching `if
12 | `else
| ^~~~~
%Error: t/t_preproc_elsif_bad.v:13:1: `endif with no matching `if
13 | `endif
| ^~~~~~
%Error: t/t_preproc_elsif_bad.v:15:8: Expecting `error string. Found: INCLUDE
15 | `error `include
| ^~~~~~~~
%Error: Exiting due to

20
test_regress/t/t_preproc_elsif_bad.pl Executable file
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@ -0,0 +1,20 @@
#!/usr/bin/env perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(vlt => 1);
lint(
fails => 1,
# The .vh file has the error, not the .v file
expect_filename => $Self->{golden_filename},
);
ok(1);
1;

18
test_regress/t/t_preproc_elsif_bad.v Normal file
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@ -0,0 +1,18 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2010 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
//See bug289
`elsif A
`endif
`else
`endif
`error `include
module t;
endmodule

8
test_regress/t/t_randomize.out
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@ -5,15 +5,15 @@
29 | constraint order { solve length before header; }
| ^~~~~~
%Error-UNSUPPORTED: t/t_randomize.v:32:16: Unsupported: dist :/
32 | x dist { [100:102] :/ 1, 200 := 2, 300 := 5};
32 | x dist { [100:102] :/ 1, 200 := 2, 300 := 5, 400};
| ^
%Error-UNSUPPORTED: t/t_randomize.v:32:32: Unsupported: dist :=
32 | x dist { [100:102] :/ 1, 200 := 2, 300 := 5};
32 | x dist { [100:102] :/ 1, 200 := 2, 300 := 5, 400};
| ^~~
%Error-UNSUPPORTED: t/t_randomize.v:32:42: Unsupported: dist :=
32 | x dist { [100:102] :/ 1, 200 := 2, 300 := 5};
32 | x dist { [100:102] :/ 1, 200 := 2, 300 := 5, 400};
| ^~~
%Error-UNSUPPORTED: t/t_randomize.v:32:9: Unsupported: dist
32 | x dist { [100:102] :/ 1, 200 := 2, 300 := 5};
32 | x dist { [100:102] :/ 1, 200 := 2, 300 := 5, 400};
| ^~~~
%Error: Exiting due to

2
test_regress/t/t_randomize.v
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@ -29,7 +29,7 @@ class Packet;
constraint order { solve length before header; }
constraint dis {
disable soft x;
x dist { [100:102] :/ 1, 200 := 2, 300 := 5};
x dist { [100:102] :/ 1, 200 := 2, 300 := 5, 400};
}
endclass

4
test_regress/t/t_sys_file_basic.out
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@ -1,6 +1,10 @@
[0] hello v=12345667
[0] Hello2
d: 12 12
h: 00000000014 0000000c
o: 0000000c 00000000014
b: 00000000000000000000000000001100 00000000000000000000000000001100

4
test_regress/t/t_sys_file_basic.v
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@ -59,9 +59,13 @@ module t;
i = 12;
$fwrite(file, "d: "); $fwrite(file, i); $fwrite(file, " "); $fdisplay(file, i);
$fdisplay(file);
$fwriteh(file, "h: "); $fwriteh(file, i); $fwriteh(file, " "); $fdisplayh(file, i);
$fdisplayh(file);
$fwriteo(file, "o: "); $fwriteo(file, i); $fwriteo(file, " "); $fdisplayo(file, i);
$fdisplayo(file);
$fwriteb(file, "b: "); $fwriteb(file, i); $fwriteb(file, " "); $fdisplayb(file, i);
$fdisplayb(file);
$fflush(file);
$fflush();

2
test_regress/t/t_time_print.out
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@ -1,5 +1,7 @@
[0] In top.t: Hi
Time scale of t is 1ns / 1ps
Time scale of t is 1ns / 1ps
Time scale of t is 1ns / 1ps
Time: ' 0' 10ns=10000
Time: ' 0-my-ms' 10ns=0-my-ms
Time: ' 0.0-my-ms' 10ns=0.0-my-ms

2
test_regress/t/t_time_print.v
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@ -16,6 +16,8 @@ module t;
$write("[%0t] In %m: Hi\n", $time);
$printtimescale;
$printtimescale();
$printtimescale(t);
$write("Time: '%t' 10ns=%0t\n", $time, t);
$timeformat(-3, 0, "-my-ms", 8);

5
test_regress/t/t_tri_array_bufif.v
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@ -91,8 +91,9 @@ module Test1 #(
bufif1 bufb1 (drv_1, drv_b[1], ~drv_e[1]);
bufif1 bufa2 (drv_2, drv_a[2], drv_e[2]);
bufif1 bufb2 (drv_2, drv_b[2], ~drv_e[2]);
bufif1 bufa3 (drv_3, drv_a[3], drv_e[3]);
bufif1 bufb3 (drv_3, drv_b[3], ~drv_e[3]);
bufif1
bufa3 (drv_3, drv_a[3], drv_e[3]),
bufb3 (drv_3, drv_b[3], ~drv_e[3]);
assign drv = {drv_3,drv_2,drv_1,drv_0};
endmodule