verilator/test_regress/t/t_lint_repeat_bad.out

%Warning-WIDTH: t/t_lint_repeat_bad.v:18:17: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS's VARREF 'a' generates 2 bits.
                                           : ... In instance t.sub3
   18 |    wire [0:0] b = a;
      |                 ^
                ... For warning description see https://verilator.org/warn/WIDTH?v=latest
                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
%Error: Exiting due to