verilator/test_regress/t/t_xml_first.out

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<?xml version="1.0" ?>
<!-- DESCRIPTION: Verilator output: XML representation of netlist -->
<verilator_xml>
<files>
<file id="a" filename="&lt;built-in&gt;" language="1800-2017"/>
<file id="b" filename="&lt;command-line&gt;" language="1800-2017"/>
<file id="c" filename="input.vc" language="1800-2017"/>
<file id="d" filename="t/t_xml_first.v" language="1800-2017"/>
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</files>
<module_files>
<file id="d" filename="t/t_xml_first.v" language="1800-2017"/>
</module_files>
<cells>
<cell fl="d6" loc="d,6,8,6,9" name="t" submodname="t" hier="t">
<cell fl="d19" loc="d,19,4,19,9" name="cell1" submodname="mod1__W4" hier="t.cell1"/>
<cell fl="d24" loc="d,24,6,24,11" name="cell2" submodname="mod2" hier="t.cell2"/>
</cell>
</cells>
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<netlist>
<module fl="d6" loc="d,6,8,6,9" name="t" origName="t" topModule="1">
<var fl="d12" loc="d,12,10,12,13" name="clk" dtype_id="1" dir="input" vartype="logic" origName="clk"/>
<var fl="d13" loc="d,13,16,13,17" name="d" dtype_id="2" dir="input" vartype="logic" origName="d"/>
<var fl="d14" loc="d,14,22,14,23" name="q" dtype_id="2" dir="output" vartype="logic" origName="q"/>
<var fl="d16" loc="d,16,22,16,29" name="between" dtype_id="2" vartype="logic" origName="between"/>
<instance fl="d19" loc="d,19,4,19,9" name="cell1" defName="mod1__W4" origName="cell1">
<port fl="d19" loc="d,19,12,19,13" name="q" direction="out" portIndex="1">
<varref fl="d19" loc="d,19,14,19,21" name="between" dtype_id="2"/>
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</port>
<port fl="d20" loc="d,20,12,20,15" name="clk" direction="in" portIndex="2">
<varref fl="d20" loc="d,20,42,20,45" name="clk" dtype_id="1"/>
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</port>
<port fl="d21" loc="d,21,12,21,13" name="d" direction="in" portIndex="3">
<varref fl="d21" loc="d,21,42,21,43" name="d" dtype_id="2"/>
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</port>
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</instance>
<instance fl="d24" loc="d,24,6,24,11" name="cell2" defName="mod2" origName="cell2">
<port fl="d24" loc="d,24,14,24,15" name="d" direction="in" portIndex="1">
<varref fl="d24" loc="d,24,16,24,23" name="between" dtype_id="2"/>
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</port>
<port fl="d25" loc="d,25,14,25,15" name="q" direction="out" portIndex="2">
<varref fl="d25" loc="d,25,42,25,43" name="q" dtype_id="2"/>
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</port>
<port fl="d26" loc="d,26,14,26,17" name="clk" direction="in" portIndex="3">
<varref fl="d26" loc="d,26,42,26,45" name="clk" dtype_id="1"/>
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</port>
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</instance>
</module>
<module fl="d30" loc="d,30,8,30,12" name="mod1__W4" origName="mod1">
<var fl="d31" loc="d,31,15,31,20" name="WIDTH" dtype_id="3" vartype="logic" origName="WIDTH" param="true">
<const fl="d18" loc="d,18,18,18,19" name="32&apos;sh4" dtype_id="3"/>
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</var>
<var fl="d33" loc="d,33,24,33,27" name="clk" dtype_id="1" dir="input" vartype="logic" origName="clk"/>
<var fl="d34" loc="d,34,30,34,31" name="d" dtype_id="2" dir="input" vartype="logic" origName="d"/>
<var fl="d35" loc="d,35,30,35,31" name="q" dtype_id="2" dir="output" vartype="logic" origName="q"/>
<var fl="d38" loc="d,38,15,38,22" name="IGNORED" dtype_id="3" vartype="logic" origName="IGNORED" localparam="true">
<const fl="d38" loc="d,38,25,38,26" name="32&apos;sh1" dtype_id="3"/>
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</var>
<always fl="d40" loc="d,40,4,40,10">
<sentree fl="d40" loc="d,40,11,40,12">
<senitem fl="d40" loc="d,40,13,40,20" edgeType="POS">
<varref fl="d40" loc="d,40,21,40,24" name="clk" dtype_id="1"/>
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</senitem>
</sentree>
<assigndly fl="d41" loc="d,41,8,41,10" dtype_id="2">
<varref fl="d41" loc="d,41,11,41,12" name="d" dtype_id="2"/>
<varref fl="d41" loc="d,41,6,41,7" name="q" dtype_id="2"/>
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</assigndly>
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</always>
</module>
<module fl="d45" loc="d,45,8,45,12" name="mod2" origName="mod2">
<var fl="d47" loc="d,47,10,47,13" name="clk" dtype_id="1" dir="input" vartype="logic" origName="clk"/>
<var fl="d48" loc="d,48,16,48,17" name="d" dtype_id="2" dir="input" vartype="logic" origName="d"/>
<var fl="d49" loc="d,49,22,49,23" name="q" dtype_id="2" dir="output" vartype="logic" origName="q"/>
<contassign fl="d52" loc="d,52,13,52,14" dtype_id="2">
<varref fl="d52" loc="d,52,15,52,16" name="d" dtype_id="2"/>
<varref fl="d52" loc="d,52,11,52,12" name="q" dtype_id="2"/>
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</contassign>
</module>
<typetable fl="a0" loc="a,0,0,0,0">
<basicdtype fl="d47" loc="d,47,10,47,13" id="1" name="logic"/>
<basicdtype fl="d13" loc="d,13,10,13,11" id="2" name="logic" left="3" right="0"/>
<basicdtype fl="d18" loc="d,18,18,18,19" id="3" name="logic" left="31" right="0"/>
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</typetable>
</netlist>
</verilator_xml>