mirror of
https://github.com/verilator/verilator.git
synced 2025-04-28 11:36:56 +00:00
For internal messages, use <command-line> and <built-in> to match GCC.
This commit is contained in:
Wilson Snyder
parent
ef02678305
commit
ba9af4aabf
@ -6118,7 +6118,7 @@ private:
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AstExecGraph* m_execGraphp; // Execution MTask graph for threads>1 mode
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public:
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AstNetlist()
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: AstNode(new FileLine("AstRoot", 0))
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: AstNode(new FileLine(FileLine::builtInFilename(), 0))
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, m_typeTablep(NULL)
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, m_dollarUnitPkgp(NULL)
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, m_evalp(NULL)
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@ -28,6 +28,7 @@
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# include "V3Global.h"
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# include "V3Stats.h"
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# include "V3Config.h"
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# include "V3File.h"
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#endif
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#include <cstdarg>
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@ -68,13 +69,12 @@ int FileLineSingleton::nameToNumber(const string& filename) {
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}
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//! Support XML output
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//! Experimental. Updated to also put out the language.
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void FileLineSingleton::fileNameNumMapDumpXml(std::ostream& os) {
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os<<"<files>\n";
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for (FileNameNumMap::const_iterator it = m_namemap.begin(); it != m_namemap.end(); ++it) {
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os<<"<file id=\""<<filenameLetters(it->second)
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<<"\" filename=\""<<it->first
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<<"\" filename=\""<<V3OutFormatter::quoteNameControls(it->first, V3OutFormatter::LA_XML)
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<<"\" language=\""<<numberToLang(it->second).ascii()<<"\"/>\n";
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}
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os<<"</files>\n";
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@ -86,7 +86,7 @@ void FileLineSingleton::fileNameNumMapDumpXml(std::ostream& os) {
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FileLine::FileLine(FileLine::EmptySecret) {
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// Sort of a singleton
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m_lineno = 0;
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m_filenameno = singleton().nameToNumber("AstRoot");
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m_filenameno = singleton().nameToNumber(FileLine::builtInFilename());
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m_parent = NULL;
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m_warnOn = 0;
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@ -130,7 +130,7 @@ public:
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string ascii() const;
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const string filename() const { return singleton().numberToName(m_filenameno); }
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bool filenameIsGlobal() const { return (filename() == commandLineFilename()
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|| filename() == internalDefineFilename()); }
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|| filename() == builtInFilename()); }
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const string filenameLetters() const { return singleton().filenameLetters(m_filenameno); }
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const string filebasename() const;
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const string filebasenameNoExt() const;
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@ -155,8 +155,9 @@ public:
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void tracingOn(bool flag) { warnOn(V3ErrorCode::I_TRACING, flag); }
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// METHODS - Global
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static string commandLineFilename() { return "COMMAND_LINE"; }
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static string internalDefineFilename() { return "INTERNAL_VERILATOR_DEFINE"; }
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// <command-line> and <built-in> match what GCC outputs
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static string commandLineFilename() { return "<command-line>"; }
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static string builtInFilename() { return "<built-in>"; }
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static void globalWarnLintOff(bool flag) {
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defaultFileLine().warnLintOff(flag); }
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static void globalWarnStyleOff(bool flag) {
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@ -38,7 +38,7 @@ void test(const string& lhss, const string& op, const string& rhss, const string
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char* r1 = strdup(rhss.c_str());
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char* e1 = strdup(exps.c_str());
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FileLine fl = new FileLine(FileLine::internalDefineFinename(), 0);
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FileLine fl = new FileLine(FileLine::builtInFinename(), 0);
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V3Number lhnum (fl, l1);
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V3Number rhnum (fl, r1);
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@ -64,7 +64,7 @@ protected:
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s_preprocp = V3PreProc::createPreProc(cmdfl);
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s_preprocp->debug(debug());
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// Default defines
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FileLine* prefl = new FileLine(FileLine::internalDefineFilename(), 0);
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FileLine* prefl = new FileLine(FileLine::builtInFilename(), 0);
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s_preprocp->defineCmdLine(prefl, "VERILATOR", "1"); // LEAK_OK
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s_preprocp->defineCmdLine(prefl, "verilator", "1"); // LEAK_OK
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s_preprocp->defineCmdLine(prefl, "verilator3", "1"); // LEAK_OK
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@ -2,78 +2,77 @@
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<!-- DESCRIPTION: Verilator output: XML representation of netlist -->
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<verilator_xml>
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<files>
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<file id="a" filename="AstRoot" language="1800-2017"/>
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<file id="b" filename="COMMAND_LINE" language="1800-2017"/>
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<file id="c" filename="INTERNAL_VERILATOR_DEFINE" language="1800-2017"/>
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<file id="d" filename="input.vc" language="1800-2017"/>
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<file id="e" filename="t/t_xml_first.v" language="1800-2017"/>
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<file id="a" filename="<built-in>" language="1800-2017"/>
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<file id="b" filename="<command-line>" language="1800-2017"/>
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<file id="c" filename="input.vc" language="1800-2017"/>
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<file id="d" filename="t/t_xml_first.v" language="1800-2017"/>
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</files>
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<module_files>
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<file id="e" filename="t/t_xml_first.v" language="1800-2017"/>
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<file id="d" filename="t/t_xml_first.v" language="1800-2017"/>
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</module_files>
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<cells>
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<cell fl="e6" name="t" submodname="t" hier="t">
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<cell fl="e18" name="cell1" submodname="mod1" hier="t.cell1"/>
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<cell fl="e24" name="cell2" submodname="mod2" hier="t.cell2"/>
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<cell fl="d6" name="t" submodname="t" hier="t">
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<cell fl="d18" name="cell1" submodname="mod1" hier="t.cell1"/>
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<cell fl="d24" name="cell2" submodname="mod2" hier="t.cell2"/>
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</cell>
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</cells>
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<netlist>
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<module fl="e6" name="t" origName="t" topModule="1">
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<var fl="e12" name="clk" dtype_id="1" dir="input" vartype="logic" origName="clk"/>
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<var fl="e13" name="d" dtype_id="2" dir="input" vartype="logic" origName="d"/>
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<var fl="e14" name="q" dtype_id="2" dir="output" vartype="logic" origName="q"/>
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<var fl="e16" name="between" dtype_id="2" vartype="logic" origName="between"/>
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<instance fl="e18" name="cell1" defName="mod1" origName="cell1">
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<port fl="e18" name="q" direction="out" portIndex="1">
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<varref fl="e18" name="between" dtype_id="2"/>
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<module fl="d6" name="t" origName="t" topModule="1">
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<var fl="d12" name="clk" dtype_id="1" dir="input" vartype="logic" origName="clk"/>
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<var fl="d13" name="d" dtype_id="2" dir="input" vartype="logic" origName="d"/>
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<var fl="d14" name="q" dtype_id="2" dir="output" vartype="logic" origName="q"/>
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<var fl="d16" name="between" dtype_id="2" vartype="logic" origName="between"/>
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<instance fl="d18" name="cell1" defName="mod1" origName="cell1">
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<port fl="d18" name="q" direction="out" portIndex="1">
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<varref fl="d18" name="between" dtype_id="2"/>
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</port>
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<port fl="e21" name="clk" direction="in" portIndex="2">
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<varref fl="e21" name="clk" dtype_id="1"/>
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<port fl="d21" name="clk" direction="in" portIndex="2">
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<varref fl="d21" name="clk" dtype_id="1"/>
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</port>
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<port fl="e22" name="d" direction="in" portIndex="3">
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<varref fl="e22" name="d" dtype_id="2"/>
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<port fl="d22" name="d" direction="in" portIndex="3">
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<varref fl="d22" name="d" dtype_id="2"/>
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</port>
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</instance>
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<instance fl="e24" name="cell2" defName="mod2" origName="cell2">
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<port fl="e24" name="d" direction="in" portIndex="1">
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<varref fl="e24" name="between" dtype_id="2"/>
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<instance fl="d24" name="cell2" defName="mod2" origName="cell2">
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<port fl="d24" name="d" direction="in" portIndex="1">
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<varref fl="d24" name="between" dtype_id="2"/>
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</port>
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<port fl="e27" name="q" direction="out" portIndex="2">
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<varref fl="e27" name="q" dtype_id="2"/>
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<port fl="d27" name="q" direction="out" portIndex="2">
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<varref fl="d27" name="q" dtype_id="2"/>
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</port>
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<port fl="e29" name="clk" direction="in" portIndex="3">
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<varref fl="e29" name="clk" dtype_id="1"/>
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<port fl="d29" name="clk" direction="in" portIndex="3">
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<varref fl="d29" name="clk" dtype_id="1"/>
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</port>
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</instance>
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</module>
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<module fl="e33" name="mod1" origName="mod1">
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<var fl="e35" name="clk" dtype_id="1" dir="input" vartype="logic" origName="clk"/>
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<var fl="e36" name="d" dtype_id="2" dir="input" vartype="logic" origName="d"/>
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<var fl="e37" name="q" dtype_id="2" dir="output" vartype="logic" origName="q"/>
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<always fl="e39">
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<sentree fl="e39">
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<senitem fl="e39" edgeType="POS">
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<varref fl="e39" name="clk" dtype_id="1"/>
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<module fl="d33" name="mod1" origName="mod1">
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<var fl="d35" name="clk" dtype_id="1" dir="input" vartype="logic" origName="clk"/>
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<var fl="d36" name="d" dtype_id="2" dir="input" vartype="logic" origName="d"/>
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<var fl="d37" name="q" dtype_id="2" dir="output" vartype="logic" origName="q"/>
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<always fl="d39">
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<sentree fl="d39">
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<senitem fl="d39" edgeType="POS">
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<varref fl="d39" name="clk" dtype_id="1"/>
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</senitem>
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</sentree>
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<assigndly fl="e40" dtype_id="2">
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<varref fl="e40" name="d" dtype_id="2"/>
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<varref fl="e40" name="q" dtype_id="2"/>
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<assigndly fl="d40" dtype_id="2">
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<varref fl="d40" name="d" dtype_id="2"/>
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<varref fl="d40" name="q" dtype_id="2"/>
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</assigndly>
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</always>
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</module>
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<module fl="e44" name="mod2" origName="mod2">
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<var fl="e46" name="clk" dtype_id="1" dir="input" vartype="logic" origName="clk"/>
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<var fl="e47" name="d" dtype_id="2" dir="input" vartype="logic" origName="d"/>
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<var fl="e48" name="q" dtype_id="2" dir="output" vartype="logic" origName="q"/>
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<contassign fl="e51" dtype_id="2">
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<varref fl="e51" name="d" dtype_id="2"/>
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<varref fl="e51" name="q" dtype_id="2"/>
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<module fl="d44" name="mod2" origName="mod2">
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<var fl="d46" name="clk" dtype_id="1" dir="input" vartype="logic" origName="clk"/>
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<var fl="d47" name="d" dtype_id="2" dir="input" vartype="logic" origName="d"/>
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<var fl="d48" name="q" dtype_id="2" dir="output" vartype="logic" origName="q"/>
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<contassign fl="d51" dtype_id="2">
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<varref fl="d51" name="d" dtype_id="2"/>
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<varref fl="d51" name="q" dtype_id="2"/>
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</contassign>
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</module>
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<typetable fl="a0">
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<basicdtype fl="e46" id="1" name="logic"/>
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<basicdtype fl="e13" id="2" name="logic" left="3" right="0"/>
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<basicdtype fl="d46" id="1" name="logic"/>
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<basicdtype fl="d13" id="2" name="logic" left="3" right="0"/>
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</typetable>
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</netlist>
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</verilator_xml>
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@ -2,82 +2,81 @@
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<!-- DESCRIPTION: Verilator output: XML representation of netlist -->
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<verilator_xml>
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<files>
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<file id="a" filename="AstRoot" language="1800-2017"/>
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<file id="b" filename="COMMAND_LINE" language="1800-2017"/>
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<file id="c" filename="INTERNAL_VERILATOR_DEFINE" language="1800-2017"/>
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<file id="d" filename="input.vc" language="1800-2017"/>
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<file id="e" filename="t/t_xml_tag.v" language="1800-2017"/>
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<file id="a" filename="<built-in>" language="1800-2017"/>
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<file id="b" filename="<command-line>" language="1800-2017"/>
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<file id="c" filename="input.vc" language="1800-2017"/>
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<file id="d" filename="t/t_xml_tag.v" language="1800-2017"/>
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</files>
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<module_files>
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<file id="e" filename="t/t_xml_tag.v" language="1800-2017"/>
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<file id="d" filename="t/t_xml_tag.v" language="1800-2017"/>
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</module_files>
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<cells>
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<cell fl="e11" name="m" submodname="m" hier="m">
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<cell fl="e28" name="itop" submodname="ifc" hier="m.itop"/>
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<cell fl="d11" name="m" submodname="m" hier="m">
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<cell fl="d28" name="itop" submodname="ifc" hier="m.itop"/>
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</cell>
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</cells>
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<netlist>
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<module fl="e11" name="m" origName="m" topModule="1">
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<var fl="e13" name="clk_ip" tag="clk_ip" dtype_id="1" dir="input" vartype="logic" origName="clk_ip"/>
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<var fl="e14" name="rst_ip" dtype_id="1" dir="input" vartype="logic" origName="rst_ip"/>
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<var fl="e15" name="foo_op" tag="foo_op" dtype_id="1" dir="output" vartype="logic" origName="foo_op"/>
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<typedef fl="e19" name="my_struct" tag="my_struct" dtype_id="2"/>
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<instance fl="e28" name="itop" defName="ifc" origName="itop"/>
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<var fl="e28" name="itop__Viftop" dtype_id="3" vartype="ifaceref" origName="itop__Viftop"/>
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<var fl="e30" name="this_struct" tag="this_struct" dtype_id="4" vartype="" origName="this_struct"/>
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<var fl="e32" name="dotted" dtype_id="5" vartype="logic" origName="dotted"/>
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<contassign fl="e32" dtype_id="5">
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<varxref fl="e32" name="value" dtype_id="6" dotted="itop"/>
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<varref fl="e32" name="dotted" dtype_id="5"/>
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<module fl="d11" name="m" origName="m" topModule="1">
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<var fl="d13" name="clk_ip" tag="clk_ip" dtype_id="1" dir="input" vartype="logic" origName="clk_ip"/>
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<var fl="d14" name="rst_ip" dtype_id="1" dir="input" vartype="logic" origName="rst_ip"/>
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<var fl="d15" name="foo_op" tag="foo_op" dtype_id="1" dir="output" vartype="logic" origName="foo_op"/>
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<typedef fl="d19" name="my_struct" tag="my_struct" dtype_id="2"/>
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<instance fl="d28" name="itop" defName="ifc" origName="itop"/>
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<var fl="d28" name="itop__Viftop" dtype_id="3" vartype="ifaceref" origName="itop__Viftop"/>
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<var fl="d30" name="this_struct" tag="this_struct" dtype_id="4" vartype="" origName="this_struct"/>
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<var fl="d32" name="dotted" dtype_id="5" vartype="logic" origName="dotted"/>
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<contassign fl="d32" dtype_id="5">
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<varxref fl="d32" name="value" dtype_id="6" dotted="itop"/>
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<varref fl="d32" name="dotted" dtype_id="5"/>
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</contassign>
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<func fl="e34" name="f" dtype_id="1">
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<var fl="e34" name="f" dtype_id="1" dir="output" vartype="logic" origName="f"/>
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<var fl="e34" name="m" dtype_id="7" dir="input" vartype="string" origName="m"/>
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<display fl="e35" displaytype="$display">
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<sformatf fl="e35" name="%@" dtype_id="7">
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<varref fl="e35" name="m" dtype_id="7"/>
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<func fl="d34" name="f" dtype_id="1">
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<var fl="d34" name="f" dtype_id="1" dir="output" vartype="logic" origName="f"/>
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<var fl="d34" name="m" dtype_id="7" dir="input" vartype="string" origName="m"/>
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<display fl="d35" displaytype="$display">
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<sformatf fl="d35" name="%@" dtype_id="7">
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<varref fl="d35" name="m" dtype_id="7"/>
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</sformatf>
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</display>
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</func>
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<initial fl="e38">
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<begin fl="e38">
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<taskref fl="e40" name="f">
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<arg fl="e40">
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<const fl="e40" name=""	   !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~€‚ƒ„…†‡ˆ‰Š‹ŒŽ‘’“”•–—˜™š›œžŸ ¡¢£¤¥¦§¨©ª«¬­®¯°±²³´µ¶·¸¹º»¼½¾¿ÀÁÂÃÄÅÆÇÈÉÊËÌÍÎÏÐÑÒÓÔÕÖ×ØÙÚÛÜÝÞßàáâãäåæçèéêëìíîïðñòóôõö÷øùúûüýþÿ"" dtype_id="7"/>
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<initial fl="d38">
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<begin fl="d38">
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<taskref fl="d40" name="f">
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<arg fl="d40">
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<const fl="d40" name=""	   !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~€‚ƒ„…†‡ˆ‰Š‹ŒŽ‘’“”•–—˜™š›œžŸ ¡¢£¤¥¦§¨©ª«¬­®¯°±²³´µ¶·¸¹º»¼½¾¿ÀÁÂÃÄÅÆÇÈÉÊËÌÍÎÏÐÑÒÓÔÕÖ×ØÙÚÛÜÝÞßàáâãäåæçèéêëìíîïðñòóôõö÷øùúûüýþÿ"" dtype_id="7"/>
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</arg>
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</taskref>
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</begin>
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</initial>
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</module>
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<iface fl="e6" name="ifc" origName="ifc">
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<var fl="e7" name="value" dtype_id="6" vartype="integer" origName="value"/>
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<modport fl="e8" name="out_modport">
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<modportvarref fl="e8" name="value" direction="out"/>
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<iface fl="d6" name="ifc" origName="ifc">
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<var fl="d7" name="value" dtype_id="6" vartype="integer" origName="value"/>
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<modport fl="d8" name="out_modport">
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<modportvarref fl="d8" name="value" direction="out"/>
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</modport>
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</iface>
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<typetable fl="a0">
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<basicdtype fl="e30" id="5" name="logic" left="31" right="0"/>
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<basicdtype fl="e7" id="6" name="integer" left="31" right="0"/>
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<basicdtype fl="e13" id="1" name="logic"/>
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||||
<structdtype fl="e19" id="2" name="m.my_struct">
|
||||
<memberdtype fl="e20" id="8" name="clk" tag="this is clk" sub_dtype_id="9"/>
|
||||
<memberdtype fl="e21" id="10" name="k" sub_dtype_id="11"/>
|
||||
<memberdtype fl="e22" id="12" name="enable" tag="enable" sub_dtype_id="13"/>
|
||||
<memberdtype fl="e23" id="14" name="data" tag="data" sub_dtype_id="15"/>
|
||||
<basicdtype fl="d30" id="5" name="logic" left="31" right="0"/>
|
||||
<basicdtype fl="d7" id="6" name="integer" left="31" right="0"/>
|
||||
<basicdtype fl="d13" id="1" name="logic"/>
|
||||
<structdtype fl="d19" id="2" name="m.my_struct">
|
||||
<memberdtype fl="d20" id="8" name="clk" tag="this is clk" sub_dtype_id="9"/>
|
||||
<memberdtype fl="d21" id="10" name="k" sub_dtype_id="11"/>
|
||||
<memberdtype fl="d22" id="12" name="enable" tag="enable" sub_dtype_id="13"/>
|
||||
<memberdtype fl="d23" id="14" name="data" tag="data" sub_dtype_id="15"/>
|
||||
</structdtype>
|
||||
<basicdtype fl="e20" id="9" name="logic"/>
|
||||
<basicdtype fl="e21" id="11" name="logic"/>
|
||||
<basicdtype fl="e22" id="13" name="logic"/>
|
||||
<basicdtype fl="e23" id="15" name="logic"/>
|
||||
<ifacerefdtype fl="e28" id="3" modportname=""/>
|
||||
<unpackarraydtype fl="e30" id="4" sub_dtype_id="2">
|
||||
<range fl="e30">
|
||||
<const fl="e30" name="32'h1" dtype_id="5"/>
|
||||
<const fl="e30" name="32'h0" dtype_id="5"/>
|
||||
<basicdtype fl="d20" id="9" name="logic"/>
|
||||
<basicdtype fl="d21" id="11" name="logic"/>
|
||||
<basicdtype fl="d22" id="13" name="logic"/>
|
||||
<basicdtype fl="d23" id="15" name="logic"/>
|
||||
<ifacerefdtype fl="d28" id="3" modportname=""/>
|
||||
<unpackarraydtype fl="d30" id="4" sub_dtype_id="2">
|
||||
<range fl="d30">
|
||||
<const fl="d30" name="32'h1" dtype_id="5"/>
|
||||
<const fl="d30" name="32'h0" dtype_id="5"/>
|
||||
</range>
|
||||
</unpackarraydtype>
|
||||
<refdtype fl="e30" id="16" name="my_struct" sub_dtype_id="2"/>
|
||||
<basicdtype fl="e34" id="7" name="string"/>
|
||||
<refdtype fl="d30" id="16" name="my_struct" sub_dtype_id="2"/>
|
||||
<basicdtype fl="d34" id="7" name="string"/>
|
||||
</typetable>
|
||||
</netlist>
|
||||
</verilator_xml>
|
||||
|
||||
Loading…
Reference in New Issue
Block a user