verilator/test_regress/t/t_sv_cpu_code/timescale.sv

// DESCRIPTION: Verilator: Large test for SystemVerilog

// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012.

// Contributed by M W Lund, Atmel Corporation.

// **** Set simulation time scale ****
`timescale 1ns/1ps
Tests: Remove CRs. 2019-06-05 00:37:16 +00:00			`// DESCRIPTION: Verilator: Large test for SystemVerilog`

			`// This file ONLY is placed into the Public Domain, for any use,`
			`// without warranty, 2012.`

			`// Contributed by M W Lund, Atmel Corporation.`

			`// ** Set simulation time scale **`
			`timescale 1ns/1ps