verilator/test_regress/t/t_flag_werror_bad1.out

%Warning-WIDTH: t/t_flag_werror.v:10:19: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's CONST '6'h2e' generates 6 bits.
                                       : ... In instance t
   10 |    wire [3:0] foo = 6'h2e;
      |                   ^
                ... For warning description see https://verilator.org/warn/WIDTH?v=latest
                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
%Error: Exiting due to