forked from github/verilator
13 lines
295 B
Systemverilog
13 lines
295 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
|
|
//
|
|
// This file ONLY is placed under the Creative Commons Public Domain, for
|
|
// any use, without warranty, 2023 by Wilson Snyder.
|
|
// SPDX-License-Identifier: CC0-1.0
|
|
|
|
module t;
|
|
task tsk;
|
|
endtask
|
|
|
|
initial tsk.bad_missing_ref = 0;
|
|
endmodule
|