forked from github/verilator
13 lines
295 B
Systemverilog
13 lines
295 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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task tsk;
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endtask
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initial tsk.bad_missing_ref = 0;
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endmodule
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